bslathi19
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bslathi19 commented on issue bslathi19/verilog6502#1 2026-04-26 08:55:39 -07:00
32 Bit address support

The BRK changes are added in 9476c6a0dd3bec6bf7d521cdd2c3467bcd3fb929

Now that we have those, we need to update the JMP state, since it is only waiting 1 cycle for an address ![image.png](/attac…

bslathi19 created branch 32bit in bslathi19/verilog6502 2026-04-26 08:54:14 -07:00
bslathi19 pushed to 32bit at bslathi19/verilog6502 2026-04-26 08:54:14 -07:00
9476c6a0dd Add 32 bit BRK
bslathi19 commented on issue bslathi19/verilog6502#1 2026-04-25 22:54:43 -07:00
32 Bit address support

Actually before we do that, we need to do the vectors so that we can even reset the chip. We start in state BRK0 https://git.byronlathi.com/bslathi19/verilog6502/src/commit/06f933fa56fb4a83ef4580…

bslathi19 commented on issue bslathi19/verilog6502#1 2026-04-25 22:33:11 -07:00
32 Bit address support

second state that needs changed is ABSn

currently there are 2 states, for loading 2 bytes 06f933fa56/…

bslathi19 commented on issue bslathi19/verilog6502#1 2026-04-25 22:18:30 -07:00
32 Bit address support

Starting from the top, the first thing that needs to change is state IND0

All IND0 does is go to INDX1, bypassing the INDX0 state where the zp address is added with the X register. This…

bslathi19 opened issue bslathi19/verilog6502#1 2026-04-25 22:11:06 -07:00
32 Bit address support
bslathi19 pushed to master at bslathi19/fpga6502 2026-04-18 19:20:00 -07:00
470bbc39ec Grand refactor
bslathi19 pushed to master at bslathi19/fpga6502 2026-04-18 18:55:45 -07:00
ef6b5f0669 Factor out verilog6502 into its own submodule
bslathi19 pushed to master at bslathi19/verilog6502 2026-04-18 18:55:12 -07:00
06f933fa56 Factor out verilog-6502 submodule
bslathi19 created branch master in bslathi19/verilog6502 2026-04-18 18:50:48 -07:00
bslathi19 pushed to master at bslathi19/verilog6502 2026-04-18 18:50:48 -07:00
db61ca2d74 Create project
bslathi19 created repository bslathi19/verilog6502 2026-04-18 18:50:40 -07:00
bslathi19 pushed to master at bslathi19/fpga6502 2026-04-18 18:40:35 -07:00
048af1c341 Add external memory
bslathi19 created branch master in bslathi19/fpga6502 2026-04-18 16:19:47 -07:00
bslathi19 pushed to master at bslathi19/fpga6502 2026-04-18 16:19:47 -07:00
756b96d9e2 Kinda working
50f8791588 initial commit
bslathi19 created repository bslathi19/fpga6502 2026-04-18 16:19:26 -07:00
bslathi19 pushed to master at third-party/verilog-6502 2026-04-18 16:02:50 -07:00
8f19e45b40 Add WAI instruction
bslathi19 created branch master in third-party/verilog-6502 2026-04-18 16:02:23 -07:00
bslathi19 pushed to master at third-party/verilog-6502 2026-04-18 16:02:23 -07:00
ef2cc5ab45 Merge pull request #1 from willisblackburn/master
6b47307d48 Applied fix to DIHOLD logic that was already applied to original cpu.v core
a5f605d00d 65C02: fix a bug with TSB/TRB when RDY used
4f141c7a13 Merge remote-tracking branch 'upstream/master'
fec47c5427 Fix synthesis warnings, add SYNC output
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