bslathi19

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• Joined on 2025-11-07

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bslathi19 created pull request bslathi19/fpga-sim#1 2025-11-09 14:09:45 -08:00

dev/trace_fst

bslathi19 pushed to dev/trace_fst at bslathi19/fpga-sim 2025-11-09 14:00:55 -08:00

2d3d02eee9 Try 2

bslathi19 pushed to dev/trace_fst at bslathi19/fpga-sim 2025-11-09 13:45:04 -08:00

de3205bda7 Trace FST

bslathi19 created branch dev/trace_fst in bslathi19/fpga-sim 2025-11-09 13:43:00 -08:00

bslathi19 pushed to dev/trace_fst at bslathi19/fpga-sim 2025-11-09 13:43:00 -08:00

06975ff37f Trace FST

bslathi19 commented on issue bslathi19/alibaba_pcie#1 2025-11-09 00:12:41 -08:00

PCIe DMA

For simplicity, read and write will have their own sections.

bslathi19 commented on issue bslathi19/alibaba_pcie#1 2025-11-09 00:04:36 -08:00

PCIe DMA

So the only fields we really need to do are the source and destination addresses, and the length. We can autogenerate the tag based on just a counter of packets. When we write to a certain…

bslathi19 opened issue bslathi19/alibaba_pcie#1 2025-11-09 00:03:10 -08:00

PCIe DMA

bslathi19 pushed to master at bslathi19/alibaba_pcie 2025-11-08 22:06:36 -08:00

5c4d228194 Start work on DMA thing

bslathi19 pushed to master at bslathi19/alibaba_pcie 2025-11-08 22:02:29 -08:00

9a76709aaa Add flow control interface to pcie core