Oh also the branch commands will need to take calculate a 32 bit address instead of 16 bit, so thats potentially 2 more cycles that each one will take.
We basically did BRK earlier when we did reset. RTI now works, but we should test external interrupts though just to make sure they function as expected.
Now we need to implement BRK and RTI. This should be mostly similar to JSR and RTS except that we push and pull the flags register as well.
Ah we need to use the alu_sr sel to store dimux into the shift register, so that we can use the alu to decrement the stack pointer
when the original cpu pushes the address to the stack, it has already incremented PC once, so if the addresss start at 0x200
JSR LSB MSB, the PC is pointing at MSB when we start writing. This…
we cannot use the ALU to decrease the stack pointer while also using the ALU registers to store the temporary address. What we could do is modify the shift register to take in data from DIMUX…
RTS follows a very similar pattern to JSR, except instead of pushing from the stack we read from the stack. This should be a little bit easier too.
In terms of cycle count, we have added 4 cycles making JSR/RTS take 10 cycles. This is almost double the length, but hey performance was not a goal.
What the 6502 does is use the stack pointer as temporary storage for the LSB of the jump target. We need to store 3 bytes instead of 1 though. We use the ALU to decrement the stack pointer while…
thats gonna be boring. One thing that we definitely need to test is JSR, RTS, BRK, and RTI. These involve pushing and popping more bytes to/from the stack.
I think we should have tests for every instruction which has those addressing modes. Also, we need to handle the extra cycles if there is a page crossing. Lets start at the top width ADC
Done in 2a9af9e9dcfcde47be772f659a0a8b91d71ee282
We've added all addressing modes, but not all instructions will be functional. For example, the absolute and absolute,x addressing modes are…
ok it still uses the ALU to increment the ZP pointer, so we can use the same extra adder that we added for the other ZP state.
Last one is indexed indirect, which should be easier since we don't have to add to a 32 bit number, only an 8 bit number.
dfe27d4ec783cbc8e3f03a18853f24042a6a0c89
What I ended up doing was adding another signal which could increment the address bus register. This does mean that there are two 32 bit adders, one for…