bslathi19
0 Followers · 0 Following
  • Joined on 2025-11-07
Repositories
20
 Projects Packages Public Activity Starred Repositories
bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-07-21 15:41:27 -07:00
9d0306eab3 eth: Ensure that SGMII mode is disabled when AN is disabled in 1000BASE-X modules
437ed9722e Update readme
42463cec5c eth: Add support for SGMII symbol replication in 1000BASE-X MAC+PCS
8dd509df02 eth: Add support for SGMII symbol replication to 16-bit AXIS/BASE-X decode module
bd7f9dc26b eth: Fix timestamping point for USXGMII
Compare 8 commits »
bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-07-14 20:21:18 -07:00
bc4a6d3f2a eth: Update example designs
b8419024fe eth: Fix MAC testbench
5717496b9e eth: Fix typo
6e4e001684 Update readme
674ff84176 cndm: Update example designs
Compare 58 commits »
bslathi19 pushed to master at bslathi19/crypto 2026-07-12 22:16:31 -07:00
cedec1ed1f Add new poly1305 stage
bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-06-12 01:30:58 -07:00
6e1e9c905f ci: Update cocotbext-eth
923beaf58d eth: Update timestamp handling in testbenches
8427a6c12b eth: Fix timestamp point in taxi_axis_gmii_tx
8d48453215 eth: Improve frame start/end timestamps in simulation models
22d402ee50 eth: Simulation speed optimization
Compare 5 commits »
bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-06-09 00:00:55 -07:00
2957a0ced9 Update readme
7f9e9980ce eth: Update ZCU102 example design to use BASE-X core for 1G
da63de1c43 eth: Update ZCU106 example design to use BASE-X core for 1G
e42f11f1fb eth: Update KCU105 example design to use BASE-X core for 1G
148d0987f4 eth: Parameter cleanup
Compare 18 commits »
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 20:30:51 -07:00
cdbb6a9720 Get it to ACTUALLY compile :)
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 20:09:19 -07:00
6c6c3d295b Add design doc
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 20:06:24 -07:00
a21cc4241a Get it to compile at least
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 17:13:38 -07:00
151643b2ad Get it working more
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 15:54:04 -07:00
61ee654b18 Get it roughly working
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-22 23:54:50 -07:00
aa8c4a64df First shot at happy path
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-22 22:28:17 -07:00
df25550c8a Add cache arrays and test
3ea31e40aa Last commit before I nuke it
8fd83c2563 Get it to kinda work
Compare 3 commits »
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-16 16:55:41 -07:00
62a3408eb7 Add some stuff related to cache
bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-05-12 18:41:00 -07:00
3951a565b5 Update readme
39a53f0dd7 cndm: Update designs
09c583c7be cndm_proto: Update designs
3541463c91 eth: Update example designs
0745952e14 eth: Fix testbench
Compare 57 commits »
bslathi19 commented on issue bslathi19/verilog6502#3 2026-05-09 17:18:25 -07:00
embedded vs application processor

Actually lets just make the L1 direct mapped. Thats the easiest way to ensure that the cpu can run fast enough, even if there is some thrashing.

bslathi19 commented on issue bslathi19/verilog6502#3 2026-05-09 16:50:48 -07:00
embedded vs application processor

It is very important that the lowest level cache have 0 cycle latency (aka 1 cycle access). the 6502 relies on memory accessing being extremely fast because of its lack of registers.

For cache…

bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-09 16:04:11 -07:00
042d7724ff Move everything around
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-09 16:00:41 -07:00
9e174a4f02 Move everything around
bslathi19 commented on issue bslathi19/verilog6502#3 2026-05-09 15:55:14 -07:00
embedded vs application processor

We need to create a simple MMU which has cache settings for each page. Page 0 contains zero page, so should probably always be cached. However this has considerations for later if we do multitaskin…

bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-09 15:44:41 -07:00