69c17a502b
Additional synthetic, extreme register load reuse tests future-proofing issues #2942 and #2947.
Ok we changed how branch works, so it should mostly work now. With that, I think we have everything mostly functional. Now we can work on modifying cc65 to generate code for our new target.
So it kind of works but WAI increase pc by too many, it should increment PC by 1 put it increments it by 2 instead. WAI is kind of fake, but we can add a state to decode to fix this anyway.
Oh also the branch commands will need to take calculate a 32 bit address instead of 16 bit, so thats potentially 2 more cycles that each one will take.
We basically did BRK earlier when we did reset. RTI now works, but we should test external interrupts though just to make sure they function as expected.
Now we need to implement BRK and RTI. This should be mostly similar to JSR and RTS except that we push and pull the flags register as well.