bslathi19
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  • Joined on 2025-11-07
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bslathi19 created branch blathi/soc_core in bslathi19/verilog6502 2026-05-09 15:44:40 -07:00
bslathi19 opened issue bslathi19/verilog6502#3 2026-05-09 15:43:22 -07:00
embedded vs application processor
bslathi19 closed issue bslathi19/verilog6502#1 2026-05-09 15:34:23 -07:00
32 Bit address support
bslathi19 deleted branch 32bit from bslathi19/verilog6502 2026-05-09 15:34:03 -07:00
bslathi19 merged pull request bslathi19/verilog6502#2 2026-05-09 15:34:02 -07:00
32bit
bslathi19 pushed to master at bslathi19/verilog6502 2026-05-09 15:34:02 -07:00
089df744aa 32bit (#2)
bslathi19 created pull request bslathi19/verilog6502#2 2026-05-09 15:31:07 -07:00
32bit
bslathi19 commented on issue bslathi19/verilog6502#1 2026-05-09 15:29:25 -07:00
32 Bit address support

I think this is ready to merge, works good enough.

bslathi19 pushed to 32bit at bslathi19/verilog6502 2026-05-08 23:02:54 -07:00
7827bcceeb Update wrapper to work with 32 bit addresses
bslathi19 pushed to 32bit at bslathi19/verilog6502 2026-05-08 22:07:29 -07:00
6c47ce12a5 Update assembly tests
bslathi19 pushed to 32bit at bslathi19/verilog6502 2026-05-08 09:54:33 -07:00
c4d91a1994 Add cc65 code
bslathi19 pushed to master at bslathi19/cc65 2026-05-08 09:53:08 -07:00
a5a3e40ffe Allow 32 bit segments, add .TOPBYTE pseduo instruction
bslathi19 pushed to master at bslathi19/cc65 2026-05-06 09:52:44 -07:00
8eed63fa52 First go at adding 65C032
bslathi19 created branch master in bslathi19/cc65 2026-05-05 22:30:20 -07:00
bslathi19 pushed to master at bslathi19/cc65 2026-05-05 22:30:20 -07:00
d20d99b32b Fix reverse lowercase on Apple][
8fcee1b552 Merge pull request #2958 from geon/master
c31565cd5b Fixed typos. marco -> macro
a545b4fc3e Merge pull request #2951 from avolkov76/anv-bug-2942
69c17a502b Additional synthetic, extreme register load reuse tests future-proofing issues #2942 and #2947.
Compare 10 commits »
bslathi19 created repository bslathi19/cc65 2026-05-05 22:29:57 -07:00
bslathi19 commented on issue bslathi19/verilog6502#1 2026-05-04 23:02:18 -07:00
32 Bit address support

Ok we changed how branch works, so it should mostly work now. With that, I think we have everything mostly functional. Now we can work on modifying cc65 to generate code for our new target.

bslathi19 pushed to 32bit at bslathi19/verilog6502 2026-05-04 23:00:44 -07:00
3c8df89769 Add branches
bslathi19 pushed to 32bit at bslathi19/verilog6502 2026-04-30 22:59:29 -07:00
79ce91669b Add IRQ test
bslathi19 commented on issue bslathi19/verilog6502#1 2026-04-30 22:52:25 -07:00
32 Bit address support

So it kind of works but WAI increase pc by too many, it should increment PC by 1 put it increments it by 2 instead. WAI is kind of fake, but we can add a state to decode to fix this anyway.