Gate assertions behind "PEAKRDL_ASSERTIONS define"

* wip

* reorg

* update sv int

* apb4 working

* apb3 working

* version bump + ignore runner warning

* remove redundant check

* adding log on failure

* cleaning up verilator version issue

* devcontainer

* Fix missing libpython in GitHub Actions CI environment (#21)

* Initial plan

* Install libpython in GitHub Actions for cocotb tests

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

---------

Co-authored-by: Copilot <198982749+Copilot@users.noreply.github.com>

.devcontainer/Dockerfile

@@ -0,0 +1,22 @@
+FROM verilator/verilator:latest
+
+ENV DEBIAN_FRONTEND=noninteractive
+
+RUN apt-get update && \
+    apt-get install -y --no-install-recommends \
+        python3 \
+        python3-venv \
+        python3-pip \
+        python3-dev \
+        build-essential \
+        pkg-config \
+        git \
+        curl \
+        ca-certificates && \
+    rm -rf /var/lib/apt/lists/*
+
+ENV UV_INSTALL_DIR=/usr/local/bin
+ENV UV_LINK_MODE=copy
+# Install uv globally so both VS Code and terminals can use it
+RUN curl -LsSf https://astral.sh/uv/install.sh | sh
+RUN uv --version

.devcontainer/devcontainer.json

@@ -0,0 +1,36 @@
+{
+    "name": "PeakRDL BusDecoder",
+    "build": {
+        "dockerfile": "Dockerfile"
+    },
+    "runArgs": [
+        "--init"
+    ],
+    "features": {
+        "ghcr.io/devcontainers/features/common-utils:2": {
+            "username": "vscode",
+            "uid": "1000",
+            "gid": "1000",
+            "installZsh": "false",
+            "installOhMyZsh": "false"
+        }
+    },
+    "remoteUser": "vscode",
+    "postCreateCommand": "uv sync --frozen --all-extras --group tools --group test",
+    "customizations": {
+        "vscode": {
+            "settings": {
+                "python.defaultInterpreterPath": ".venv/bin/python",
+                "terminal.integrated.shell.linux": "/bin/bash"
+            },
+            "extensions": [
+                "ms-python.python",
+                "ms-python.vscode-pylance",
+                "ms-vscode.cpptools",
+                "charliermarsh.ruff",
+                "astral-sh.ty",
+                "meta.pyrefly"
+            ]
+        }
+    }
+}

.github/workflows/release.yml

@@ -40,7 +40,6 @@ jobs:
       
       - name: Publish to PyPI
         if: startsWith(github.ref, 'refs/tags/')
-        env:
+        uses: pypa/gh-action-pypi-publish@release/v1
-          TWINE_USERNAME: __token__
+        with:
-          TWINE_PASSWORD: ${{ secrets.PYPI_API_TOKEN }}
+          skip-existing: true
-        run: uvx twine upload dist/*

.github/workflows/test.yml

@@ -7,10 +7,15 @@ on:
     branches: [ main ]
   workflow_dispatch:
   workflow_call:
+  schedule:
+    # Run weekly on Monday at 00:00 UTC
+    - cron: '0 0 * * 1'
 
 jobs:
   test:
     runs-on: ubuntu-latest
+    container:
+      image: verilator/verilator:latest
     permissions:
       contents: read
     strategy:
@@ -24,13 +29,21 @@ jobs:
         uses: astral-sh/setup-uv@v3
         with:
           python-version: ${{ matrix.python-version }}
+          enable-cache: true
+
+      - name: Check Verilator version
+        run: verilator --version
+      
+      - name: Install Python development packages
+        run: |
+          apt-get update && apt-get install -y python3-dev libpython3-dev
       
       - name: Install dependencies
         run: |
-          uv sync --group test
+          uv sync --all-extras --group test
       
       - name: Run tests
-        run: uv run pytest tests/ -v --cov=peakrdl_busdecoder --cov-report=xml --cov-report=term
+        run: uv run pytest tests/ --cov=peakrdl_busdecoder --cov-report=xml --cov-report=term
       
       - name: Upload coverage to Codecov
         uses: codecov/codecov-action@v4

hdl-src/apb3_intf.sv

@@ -2,6 +2,10 @@ interface apb3_intf #(
     parameter DATA_WIDTH = 32,
     parameter ADDR_WIDTH = 32
 );
+    // Clocking
+    logic PCLK;
+    logic PRESETn;
+
     // Command
     logic PSEL;
     logic PENABLE;
@@ -15,6 +19,9 @@ interface apb3_intf #(
     logic PSLVERR;
 
     modport master (
+        input PCLK,
+        input PRESETn,
+
         output PSEL,
         output PENABLE,
         output PWRITE,
@@ -27,6 +34,9 @@ interface apb3_intf #(
     );
 
     modport slave (
+        input PCLK,
+        input PRESETn,
+
         input PSEL,
         input PENABLE,
         input PWRITE,

hdl-src/apb4_intf.sv

@@ -2,6 +2,10 @@ interface apb4_intf #(
     parameter DATA_WIDTH = 32,
     parameter ADDR_WIDTH = 32
 );
+    // Clocking
+    logic PCLK;
+    logic PRESETn;
+
     // Command
     logic PSEL;
     logic PENABLE;
@@ -17,6 +21,9 @@ interface apb4_intf #(
     logic PSLVERR;
 
     modport master (
+        input PCLK,
+        input PRESETn,
+
         output PSEL,
         output PENABLE,
         output PWRITE,
@@ -31,6 +38,9 @@ interface apb4_intf #(
     );
 
     modport slave (
+        input PCLK,
+        input PRESETn,
+
         input PSEL,
         input PENABLE,
         input PWRITE,

hdl-src/axi4lite_intf.sv

@@ -2,6 +2,9 @@ interface axi4lite_intf #(
     parameter DATA_WIDTH = 32,
     parameter ADDR_WIDTH = 32
 );
+    logic ACLK;
+    logic ARESETn;
+
     logic AWREADY;
     logic AWVALID;
     logic [ADDR_WIDTH-1:0] AWADDR;
@@ -27,6 +30,9 @@ interface axi4lite_intf #(
     logic [1:0] RRESP;
 
     modport master (
+        input ACLK,
+        input ARESETn,
+
         input AWREADY,
         output AWVALID,
         output AWADDR,
@@ -53,15 +59,18 @@ interface axi4lite_intf #(
     );
 
     modport slave (
+        input ACLK,
+        input ARESETn,
+
         output AWREADY,
-        // input AWVALID,
+        input AWVALID,
-        // input AWADDR,
+        input AWADDR,
         input AWPROT,
 
         output WREADY,
-        // input WVALID,
+        input WVALID,
-        // input WDATA,
+        input WDATA,
-        // input WSTRB,
+        input WSTRB,
 
         input BREADY,
         output BVALID,
@@ -73,8 +82,8 @@ interface axi4lite_intf #(
         input ARPROT,
 
         input RREADY,
-        // output RVALID,
+        output RVALID,
-        // output RDATA,
+        output RDATA,
-        // output RRESP
+        output RRESP
     );
 endinterface

pyproject.toml

@@ -4,11 +4,11 @@ build-backend = "setuptools.build_meta"
 
 [project]
 name = "peakrdl-busdecoder"
-version = "0.1.0"
+version = "0.6.0"
 requires-python = ">=3.10"
-dependencies = ["jinja2>=3.1.6", "systemrdl-compiler~=1.30.1"]
+dependencies = ["jinja2>=3.1.6", "systemrdl-compiler~=1.31"]
 
-authors = [{ name = "Alex Mykyta" }]
+authors = [{ name = "Arnav Sacheti" }]
 description = "Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces"
 readme = "README.md"
 license = { text = "LGPLv3" }
@@ -59,13 +59,15 @@ test = [
     "pytest>=7.4.4",
     "pytest-cov>=4.1.0",
     "pytest-xdist>=3.5.0",
+    "cocotb>=1.8.0",
+    "cocotb-bus>=0.2.1",
 ]
 tools = ["pyrefly>=0.37.0", "ruff>=0.14.0"]
 
 [project.entry-points."peakrdl.exporters"]
 busdecoder = "peakrdl_busdecoder.__peakrdl__:Exporter"
 
-
+# ---------------------- RUFF ----------------------
 [tool.ruff]
 line-length = 110
 target-version = "py310"
@@ -102,5 +104,14 @@ python-version = "3.10"
 # Default behavior: check bodies of untyped defs & infer return types.
 untyped-def-behavior = "check-and-infer-return-type"
 
-project-includes = ["**/*"]
+project-includes = ["src/**/*"]
 project-excludes = ["**/__pycache__", "**/*venv/**/*"]
+
+# ---------------------- PYTEST ----------------------
+[tool.pytest.ini_options]
+python_files = ["test_*.py", "*_test.py"]
+markers = [
+    "simulation: marks tests as requiring cocotb simulation (deselect with '-m \"not simulation\"')",
+    "verilator: marks tests as requiring verilator simulator (deselect with '-m \"not verilator\"')",
+]
+filterwarnings = ["error", "ignore::UserWarning"]

src/peakrdl_busdecoder/__peakrdl__.py

@@ -5,7 +5,7 @@ from peakrdl.config import schema
 from peakrdl.plugins.entry_points import get_entry_points
 from peakrdl.plugins.exporter import ExporterSubcommandPlugin
 
-from .cpuif import BaseCpuif, apb3, apb4, axi4lite
+from .cpuif import BaseCpuif, apb3, apb4, axi4lite, taxi_apb
 from .exporter import BusDecoderExporter
 from .udps import ALL_UDPS
 
@@ -24,6 +24,7 @@ def get_cpuifs(config: list[tuple[str, Any]]) -> dict[str, type[BaseCpuif]]:
         "apb3-flat": apb3.APB3CpuifFlat,
         "apb4": apb4.APB4Cpuif,
         "apb4-flat": apb4.APB4CpuifFlat,
+        "taxi-apb": taxi_apb.TaxiAPBCpuif,
         "axi4-lite": axi4lite.AXI4LiteCpuif,
         "axi4-lite-flat": axi4lite.AXI4LiteCpuifFlat,
     }
@@ -111,6 +112,17 @@ class Exporter(ExporterSubcommandPlugin):
             """,
         )
 
+        arg_group.add_argument(
+            "--max-decode-depth",
+            type=int,
+            default=1,
+            help="""Maximum depth for address decoder to descend into nested
+            addressable components. Value of 0 decodes all levels (infinite depth).
+            Value of 1 decodes only top-level children. Value of 2 decodes top-level
+            and one level deeper, etc. Default is 1.
+            """,
+        )
+
     def do_export(self, top_node: "AddrmapNode", options: "argparse.Namespace") -> None:
         cpuifs = self.get_cpuifs()
 
@@ -123,4 +135,5 @@ class Exporter(ExporterSubcommandPlugin):
             package_name=options.package_name,
             address_width=options.addr_width,
             cpuif_unroll=options.unroll,
+            max_decode_depth=options.max_decode_depth,
         )

src/peakrdl_busdecoder/body/if_body.py

@@ -1,5 +1,3 @@
-from __future__ import annotations
-
 from textwrap import indent
 from types import EllipsisType
 
@@ -50,7 +48,7 @@ class IfBody(Body):
 
     # --- Context manager for a branch ---
     class _BranchCtx:
-        def __init__(self, outer: IfBody, condition: SupportsStr | None) -> None:
+        def __init__(self, outer: "IfBody", condition: SupportsStr | None) -> None:
             self._outer = outer
             # route through __getitem__ to reuse validation logic
             self._body = outer[Ellipsis if condition is None else condition]
@@ -66,7 +64,7 @@ class IfBody(Body):
         ) -> bool:
             return False
 
-    def cm(self, condition: SupportsStr | None) -> IfBody._BranchCtx:
+    def cm(self, condition: SupportsStr | None) -> "IfBody._BranchCtx":
         """Use with: with ifb.cm('cond') as b: ...  ; use None for else."""
         return IfBody._BranchCtx(self, condition)
 

src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py

@@ -1,47 +1,36 @@
-from typing import overload
+from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
 
 from ...utils import get_indexed_path
 from ..base_cpuif import BaseCpuif
+from .apb3_interface import APB3SVInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
 
 
 class APB3Cpuif(BaseCpuif):
     template_path = "apb3_tmpl.sv"
-    is_interface = True
 
-    def _port_declaration(self, child: AddressableNode) -> str:
+    def __init__(self, exp: "BusDecoderExporter") -> None:
-        base = f"apb3_intf.master m_apb_{child.inst_name}"
+        super().__init__(exp)
+        self._interface = APB3SVInterface(self)
 
-        # When unrolled, current_idx is set - append it to the name
+    @property
-        if child.current_idx is not None:
+    def is_interface(self) -> bool:
-            base = f"{base}_{'_'.join(map(str, child.current_idx))}"
+        return self._interface.is_interface
-
-        # Only add array dimensions if this should be treated as an array
-        if self.check_is_array(child):
-            assert child.array_dimensions is not None
-            return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
-
-        return base
 
     @property
     def port_declaration(self) -> str:
-        slave_ports: list[str] = ["apb3_intf.slave s_apb"]
+        return self._interface.get_port_declaration("s_apb", "m_apb_")
-        master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
-
-        return ",\n".join(slave_ports + master_ports)
 
     @overload
     def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
     @overload
     def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
-        if node is None or indexer is None:
+        return self._interface.signal(signal, node, indexer)
-            # Node is none, so this is a slave signal
-            return f"s_apb.{signal}"
-
-        # Master signal
-        return f"m_apb_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}
@@ -63,8 +52,16 @@ class APB3Cpuif(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            # Use intermediate signals for interface arrays to avoid
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+            else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -73,6 +70,23 @@ class APB3Cpuif(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
+            else:
+                fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for APB3 interface arrays."""
+        return [
+            f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.PREADY;",
+            f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.PSLVERR;",
+            f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.PRDATA;",
+        ]

src/peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py

@@ -1,46 +1,29 @@
+from typing import TYPE_CHECKING
+
 from systemrdl.node import AddressableNode
 
 from ...utils import get_indexed_path
 from ..base_cpuif import BaseCpuif
+from .apb3_interface import APB3FlatInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
 
 
 class APB3CpuifFlat(BaseCpuif):
     template_path = "apb3_tmpl.sv"
-    is_interface = False
 
-    def _port_declaration(self, child: AddressableNode) -> list[str]:
+    def __init__(self, exp: "BusDecoderExporter") -> None:
-        return [
+        super().__init__(exp)
-            f"input logic {self.signal('PCLK', child)}",
+        self._interface = APB3FlatInterface(self)
-            f"input logic {self.signal('PRESETn', child)}",
+
-            f"input logic {self.signal('PSELx', child)}",
+    @property
-            f"input logic {self.signal('PENABLE', child)}",
+    def is_interface(self) -> bool:
-            f"input logic {self.signal('PWRITE', child)}",
+        return self._interface.is_interface
-            f"input logic [{self.addr_width - 1}:0] {self.signal('PADDR', child)}",
-            f"input logic [{self.data_width - 1}:0] {self.signal('PWDATA', child)}",
-            f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA', child)}",
-            f"output logic {self.signal('PREADY', child)}",
-            f"output logic {self.signal('PSLVERR', child)}",
-        ]
 
     @property
     def port_declaration(self) -> str:
-        slave_ports: list[str] = [
+        return self._interface.get_port_declaration("s_apb_", "m_apb_")
-            f"input logic {self.signal('PCLK')}",
-            f"input logic {self.signal('PRESETn')}",
-            f"input logic {self.signal('PSELx')}",
-            f"input logic {self.signal('PENABLE')}",
-            f"input logic {self.signal('PWRITE')}",
-            f"input logic [{self.addr_width - 1}:0] {self.signal('PADDR')}",
-            f"input logic [{self.data_width - 1}:0] {self.signal('PWDATA')}",
-            f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA')}",
-            f"output logic {self.signal('PREADY')}",
-            f"output logic {self.signal('PSLVERR')}",
-        ]
-        master_ports: list[str] = []
-        for child in self.addressable_children:
-            master_ports.extend(self._port_declaration(child))
-
-        return ",\n".join(slave_ports + master_ports)
 
     def signal(
         self,
@@ -48,34 +31,19 @@ class APB3CpuifFlat(BaseCpuif):
         node: AddressableNode | None = None,
         idx: str | int | None = None,
     ) -> str:
-        if node is None:
+        return self._interface.signal(signal, node, idx)
-            # Node is none, so this is a slave signal
-            return f"s_apb_{signal}"
-
-        # Master signal
-        base = f"m_apb_{node.inst_name}"
-        if not self.check_is_array(node):
-            # Not an array or an unrolled element
-            if node.current_idx is not None:
-                # This is a specific instance of an unrolled array
-                return f"{base}_{signal}_{'_'.join(map(str, node.current_idx))}"
-            return f"{base}_{signal}"
-        # Is an array
-        if idx is not None:
-            return f"{base}_{signal}[{idx}]"
-        return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}
-        fanout[self.signal("PSELx", node)] = (
+        fanout[self.signal("PSEL", node, "gi")] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
+        fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
-        fanout[self.signal("PWRITE", node)] = (
+        fanout[self.signal("PWRITE", node, "gi")] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PADDR", node)] = self.signal("PADDR")
+        fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
-        fanout[self.signal("PWDATA", node)] = "cpuif_wr_data"
+        fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
 
         return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
 
@@ -85,8 +53,8 @@ class APB3CpuifFlat(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -95,6 +63,6 @@ class APB3CpuifFlat(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

src/peakrdl_busdecoder/cpuif/apb3/apb3_interface.py

@@ -0,0 +1,56 @@
+"""APB3-specific interface implementations."""
+
+from systemrdl.node import AddressableNode
+
+from ..interface import FlatInterface, SVInterface
+
+
+class APB3SVInterface(SVInterface):
+    """APB3 SystemVerilog interface."""
+
+    def get_interface_type(self) -> str:
+        return "apb3_intf"
+
+    def get_slave_name(self) -> str:
+        return "s_apb"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+
+class APB3FlatInterface(FlatInterface):
+    """APB3 flat signal interface."""
+
+    def get_slave_prefix(self) -> str:
+        return "s_apb_"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+    def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
+        return [
+            f"input  logic {slave_prefix}PCLK",
+            f"input  logic {slave_prefix}PRESETn",
+            f"input  logic {slave_prefix}PSEL",
+            f"input  logic {slave_prefix}PENABLE",
+            f"input  logic {slave_prefix}PWRITE",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}PADDR",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PWDATA",
+            f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PRDATA",
+            f"output logic {slave_prefix}PREADY",
+            f"output logic {slave_prefix}PSLVERR",
+        ]
+
+    def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
+        return [
+            f"output logic {self.signal('PCLK', child)}",
+            f"output logic {self.signal('PRESETn', child)}",
+            f"output logic {self.signal('PSEL', child)}",
+            f"output logic {self.signal('PENABLE', child)}",
+            f"output logic {self.signal('PWRITE', child)}",
+            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('PADDR', child)}",
+            f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
+            f"input  logic {self.signal('PREADY', child)}",
+            f"input  logic {self.signal('PSLVERR', child)}",
+        ]

src/peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv

@@ -26,6 +26,13 @@ assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpu
 // Fanout CPU Bus interface signals
 //--------------------------------------------------------------------------
 {{fanout|walk(cpuif=cpuif)}}
+{%- if cpuif.is_interface %}
+
+//--------------------------------------------------------------------------
+// Intermediate signals for interface array fanin
+//--------------------------------------------------------------------------
+{{fanin_intermediate|walk(cpuif=cpuif)}}
+{%- endif %}
 
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals

src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py

@@ -1,48 +1,37 @@
-from typing import overload
+from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
 
 from ...utils import get_indexed_path
 from ..base_cpuif import BaseCpuif
+from .apb4_interface import APB4SVInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
 
 
 class APB4Cpuif(BaseCpuif):
     template_path = "apb4_tmpl.sv"
-    is_interface = True
 
-    def _port_declaration(self, child: AddressableNode) -> str:
+    def __init__(self, exp: "BusDecoderExporter") -> None:
-        base = f"apb4_intf.master m_apb_{child.inst_name}"
+        super().__init__(exp)
+        self._interface = APB4SVInterface(self)
 
-        # When unrolled, current_idx is set - append it to the name
+    @property
-        if child.current_idx is not None:
+    def is_interface(self) -> bool:
-            base = f"{base}_{'_'.join(map(str, child.current_idx))}"
+        return self._interface.is_interface
-
-        # Only add array dimensions if this should be treated as an array
-        if self.check_is_array(child):
-            assert child.array_dimensions is not None
-            return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
-
-        return base
 
     @property
     def port_declaration(self) -> str:
         """Returns the port declaration for the APB4 interface."""
-        slave_ports: list[str] = ["apb4_intf.slave s_apb"]
+        return self._interface.get_port_declaration("s_apb", "m_apb_")
-        master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
-
-        return ",\n".join(slave_ports + master_ports)
 
     @overload
     def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
     @overload
     def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
-        if node is None or indexer is None:
+        return self._interface.signal(signal, node, indexer)
-            # Node is none, so this is a slave signal
-            return f"s_apb.{signal}"
-
-        # Master signal
-        return f"m_apb_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}
@@ -66,8 +55,16 @@ class APB4Cpuif(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            # Use intermediate signals for interface arrays to avoid
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+            else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -76,6 +73,23 @@ class APB4Cpuif(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
+            else:
+                fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for APB4 interface arrays."""
+        return [
+            f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.PREADY;",
+            f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.PSLVERR;",
+            f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.PRDATA;",
+        ]

src/peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py

@@ -1,50 +1,29 @@
+from typing import TYPE_CHECKING
+
 from systemrdl.node import AddressableNode
 
-from ...utils import get_indexed_path
+from ...utils import clog2, get_indexed_path
 from ..base_cpuif import BaseCpuif
+from .apb4_interface import APB4FlatInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
 
 
 class APB4CpuifFlat(BaseCpuif):
     template_path = "apb4_tmpl.sv"
-    is_interface = False
 
-    def _port_declaration(self, child: AddressableNode) -> list[str]:
+    def __init__(self, exp: "BusDecoderExporter") -> None:
-        return [
+        super().__init__(exp)
-            f"input  logic {self.signal('PCLK', child)}",
+        self._interface = APB4FlatInterface(self)
-            f"input  logic {self.signal('PRESETn', child)}",
+
-            f"input  logic {self.signal('PSELx', child)}",
+    @property
-            f"input  logic {self.signal('PENABLE', child)}",
+    def is_interface(self) -> bool:
-            f"input  logic {self.signal('PWRITE', child)}",
+        return self._interface.is_interface
-            f"input  logic [{self.addr_width - 1}:0] {self.signal('PADDR', child)}",
-            f"input  logic [2:0] {self.signal('PPROT', child)}",
-            f"input  logic [{self.data_width - 1}:0] {self.signal('PWDATA', child)}",
-            f"input  logic [{self.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",
-            f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA', child)}",
-            f"output logic {self.signal('PREADY', child)}",
-            f"output logic {self.signal('PSLVERR', child)}",
-        ]
 
     @property
     def port_declaration(self) -> str:
-        slave_ports: list[str] = [
+        return self._interface.get_port_declaration("s_apb_", "m_apb_")
-            f"input  logic {self.signal('PCLK')}",
-            f"input  logic {self.signal('PRESETn')}",
-            f"input  logic {self.signal('PSELx')}",
-            f"input  logic {self.signal('PENABLE')}",
-            f"input  logic {self.signal('PWRITE')}",
-            f"input  logic [{self.addr_width - 1}:0] {self.signal('PADDR')}",
-            f"input  logic [2:0] {self.signal('PPROT')}",
-            f"input  logic [{self.data_width - 1}:0] {self.signal('PWDATA')}",
-            f"input  logic [{self.data_width // 8 - 1}:0] {self.signal('PSTRB')}",
-            f"output logic [{self.data_width - 1}:0] {self.signal('PRDATA')}",
-            f"output logic {self.signal('PREADY')}",
-            f"output logic {self.signal('PSLVERR')}",
-        ]
-        master_ports: list[str] = []
-        for child in self.addressable_children:
-            master_ports.extend(self._port_declaration(child))
-
-        return ",\n".join(slave_ports + master_ports)
 
     def signal(
         self,
@@ -52,36 +31,21 @@ class APB4CpuifFlat(BaseCpuif):
         node: AddressableNode | None = None,
         idx: str | int | None = None,
     ) -> str:
-        if node is None:
+        return self._interface.signal(signal, node, idx)
-            # Node is none, so this is a slave signal
-            return f"s_apb_{signal}"
-
-        # Master signal
-        base = f"m_apb_{node.inst_name}"
-        if not self.check_is_array(node):
-            # Not an array or an unrolled element
-            if node.current_idx is not None:
-                # This is a specific instance of an unrolled array
-                return f"{base}_{signal}_{'_'.join(map(str, node.current_idx))}"
-            return f"{base}_{signal}"
-        # Is an array
-        if idx is not None:
-            return f"{base}_{signal}[{idx}]"
-        return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}
-        fanout[self.signal("PSELx", node)] = (
+        fanout[self.signal("PSEL", node, "gi")] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
+        fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
-        fanout[self.signal("PWRITE", node)] = (
+        fanout[self.signal("PWRITE", node, "gi")] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PADDR", node)] = self.signal("PADDR")
+        fanout[self.signal("PADDR", node, "gi")] = f"{self.signal('PADDR')}[{clog2(node.size) - 1}:0]"
-        fanout[self.signal("PPROT", node)] = self.signal("PPROT")
+        fanout[self.signal("PPROT", node, "gi")] = self.signal("PPROT")
-        fanout[self.signal("PWDATA", node)] = "cpuif_wr_data"
+        fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
-        fanout[self.signal("PSTRB", node)] = "cpuif_wr_byte_en"
+        fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en"
 
         return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
 
@@ -91,8 +55,8 @@ class APB4CpuifFlat(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -101,6 +65,6 @@ class APB4CpuifFlat(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

src/peakrdl_busdecoder/cpuif/apb4/apb4_interface.py

@@ -0,0 +1,61 @@
+"""APB4-specific interface implementations."""
+
+from systemrdl.node import AddressableNode
+
+from ...utils import clog2
+from ..interface import FlatInterface, SVInterface
+
+
+class APB4SVInterface(SVInterface):
+    """APB4 SystemVerilog interface."""
+
+    def get_interface_type(self) -> str:
+        return "apb4_intf"
+
+    def get_slave_name(self) -> str:
+        return "s_apb"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+
+class APB4FlatInterface(FlatInterface):
+    """APB4 flat signal interface."""
+
+    def get_slave_prefix(self) -> str:
+        return "s_apb_"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"
+
+    def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
+        return [
+            f"input  logic {slave_prefix}PCLK",
+            f"input  logic {slave_prefix}PRESETn",
+            f"input  logic {slave_prefix}PSEL",
+            f"input  logic {slave_prefix}PENABLE",
+            f"input  logic {slave_prefix}PWRITE",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}PADDR",
+            f"input  logic [2:0] {slave_prefix}PPROT",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PWDATA",
+            f"input  logic [{self.cpuif.data_width // 8 - 1}:0] {slave_prefix}PSTRB",
+            f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}PRDATA",
+            f"output logic {slave_prefix}PREADY",
+            f"output logic {slave_prefix}PSLVERR",
+        ]
+
+    def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
+        return [
+            f"output logic {self.signal('PCLK', child)}",
+            f"output logic {self.signal('PRESETn', child)}",
+            f"output logic {self.signal('PSEL', child)}",
+            f"output logic {self.signal('PENABLE', child)}",
+            f"output logic {self.signal('PWRITE', child)}",
+            f"output logic [{clog2(child.size) - 1}:0] {self.signal('PADDR', child)}",
+            f"output logic [2:0] {self.signal('PPROT', child)}",
+            f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('PWDATA', child)}",
+            f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('PSTRB', child)}",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('PRDATA', child)}",
+            f"input  logic {self.signal('PREADY', child)}",
+            f"input  logic {self.signal('PSLVERR', child)}",
+        ]

src/peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv

@@ -6,8 +6,10 @@
         assert_bad_data_width: assert($bits({{cpuif.signal("PWDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("PWDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
     end
-    assert_wr_sel: assert (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
+    `ifdef PEAKRDL_ASSERTIONS
+    assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("PSEL")}} && {{cpuif.signal("PWRITE")}} |-> ##1 ({{cpuif.signal("PREADY")}} || {{cpuif.signal("PSLVERR")}}))
         else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+    `endif
 `endif
 {%- endif %}
 
@@ -29,6 +31,13 @@ assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpu
 // Fanout CPU Bus interface signals
 //--------------------------------------------------------------------------
 {{fanout|walk(cpuif=cpuif)}}
+{%- if cpuif.is_interface %}
+
+//--------------------------------------------------------------------------
+// Intermediate signals for interface array fanin
+//--------------------------------------------------------------------------
+{{fanin_intermediate|walk(cpuif=cpuif)}}
+{%- endif %}
 
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals

src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py

@@ -1,48 +1,37 @@
-from typing import overload
+from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
 
 from ...utils import get_indexed_path
 from ..base_cpuif import BaseCpuif
+from .axi4_lite_interface import AXI4LiteSVInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
 
 
 class AXI4LiteCpuif(BaseCpuif):
-    template_path = "axi4lite_tmpl.sv"
+    template_path = "axi4_lite_tmpl.sv"
-    is_interface = True
 
-    def _port_declaration(self, child: AddressableNode) -> str:
+    def __init__(self, exp: "BusDecoderExporter") -> None:
-        base = f"axi4lite_intf.master m_axil_{child.inst_name}"
+        super().__init__(exp)
+        self._interface = AXI4LiteSVInterface(self)
 
-        # When unrolled, current_idx is set - append it to the name
+    @property
-        if child.current_idx is not None:
+    def is_interface(self) -> bool:
-            base = f"{base}_{'_'.join(map(str, child.current_idx))}"
+        return self._interface.is_interface
-
-        # Only add array dimensions if this should be treated as an array
-        if self.check_is_array(child):
-            assert child.array_dimensions is not None
-            return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
-
-        return base
 
     @property
     def port_declaration(self) -> str:
         """Returns the port declaration for the AXI4-Lite interface."""
-        slave_ports: list[str] = ["axi4lite_intf.slave s_axil"]
+        return self._interface.get_port_declaration("s_axil", "m_axil_")
-        master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
-
-        return ",\n".join(slave_ports + master_ports)
 
     @overload
     def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
     @overload
-    def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
+    def signal(self, signal: str, node: AddressableNode, indexer: str | None = None) -> str: ...
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
-        if node is None or indexer is None:
+        return self._interface.signal(signal, node, indexer)
-            # Node is none, so this is a slave signal
-            return f"s_axil.{signal}"
-
-        # Master signal
-        return f"m_axil_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}
@@ -79,9 +68,17 @@ class AXI4LiteCpuif(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
+            # Use intermediate signals for interface arrays to avoid
-            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+            # non-constant indexing of interface arrays in procedural blocks
-            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+            else:
+                # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
+                fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+                fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
 
@@ -90,6 +87,23 @@ class AXI4LiteCpuif(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
+            else:
+                fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for AXI4-Lite interface arrays."""
+        return [
+            f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.RVALID;",
+            f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.RRESP[1];",
+            f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.RDATA;",
+        ]

src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py

@@ -1,48 +1,39 @@
-from typing import overload
+from typing import TYPE_CHECKING, overload
 
 from systemrdl.node import AddressableNode
 
 from ...utils import get_indexed_path
 from ..base_cpuif import BaseCpuif
+from .axi4_lite_interface import AXI4LiteFlatInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
 
 
 class AXI4LiteCpuifFlat(BaseCpuif):
-    template_path = "axi4lite_tmpl.sv"
+    """Verilator-friendly variant that flattens the AXI4-Lite interface ports."""
-    is_interface = True
 
-    def _port_declaration(self, child: AddressableNode) -> str:
+    template_path = "axi4_lite_tmpl.sv"
-        base = f"axi4lite_intf.master m_axil_{child.inst_name}"
 
-        # When unrolled, current_idx is set - append it to the name
+    def __init__(self, exp: "BusDecoderExporter") -> None:
-        if child.current_idx is not None:
+        super().__init__(exp)
-            base = f"{base}_{'_'.join(map(str, child.current_idx))}"
+        self._interface = AXI4LiteFlatInterface(self)
 
-        # Only add array dimensions if this should be treated as an array
+    @property
-        if self.check_is_array(child):
+    def is_interface(self) -> bool:
-            assert child.array_dimensions is not None
+        return self._interface.is_interface
-            return f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
-
-        return base
 
     @property
     def port_declaration(self) -> str:
         """Returns the port declaration for the AXI4-Lite interface."""
-        slave_ports: list[str] = ["axi4lite_intf.slave s_axil"]
+        return self._interface.get_port_declaration("s_axil_", "m_axil_")
-        master_ports: list[str] = list(map(self._port_declaration, self.addressable_children))
-
-        return ",\n".join(slave_ports + master_ports)
 
     @overload
     def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
     @overload
-    def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
+    def signal(self, signal: str, node: AddressableNode, indexer: str | None = None) -> str: ...
     def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
-        if node is None or indexer is None:
+        return self._interface.signal(signal, node, indexer)
-            # Node is none, so this is a slave signal
-            return f"s_axil.{signal}"
-
-        # Master signal
-        return f"m_axil_{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}

src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_interface.py

@@ -0,0 +1,84 @@
+"""AXI4-Lite-specific interface implementations."""
+
+from systemrdl.node import AddressableNode
+
+from ..interface import FlatInterface, SVInterface
+
+
+class AXI4LiteSVInterface(SVInterface):
+    """AXI4-Lite SystemVerilog interface."""
+
+    def get_interface_type(self) -> str:
+        return "axi4lite_intf"
+
+    def get_slave_name(self) -> str:
+        return "s_axil"
+
+    def get_master_prefix(self) -> str:
+        return "m_axil_"
+
+
+class AXI4LiteFlatInterface(FlatInterface):
+    """AXI4-Lite flat signal interface."""
+
+    def get_slave_prefix(self) -> str:
+        return "s_axil_"
+
+    def get_master_prefix(self) -> str:
+        return "m_axil_"
+
+    def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
+        return [
+            # Write address channel
+            f"input  logic {slave_prefix}AWVALID",
+            f"output logic {slave_prefix}AWREADY",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}AWADDR",
+            f"input  logic [2:0] {slave_prefix}AWPROT",
+            # Write data channel
+            f"input  logic {slave_prefix}WVALID",
+            f"output logic {slave_prefix}WREADY",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {slave_prefix}WDATA",
+            f"input  logic [{self.cpuif.data_width // 8 - 1}:0] {slave_prefix}WSTRB",
+            # Write response channel
+            f"output logic {slave_prefix}BVALID",
+            f"input  logic {slave_prefix}BREADY",
+            f"output logic [1:0] {slave_prefix}BRESP",
+            # Read address channel
+            f"input  logic {slave_prefix}ARVALID",
+            f"output logic {slave_prefix}ARREADY",
+            f"input  logic [{self.cpuif.addr_width - 1}:0] {slave_prefix}ARADDR",
+            f"input  logic [2:0] {slave_prefix}ARPROT",
+            # Read data channel
+            f"output logic {slave_prefix}RVALID",
+            f"input  logic {slave_prefix}RREADY",
+            f"output logic [{self.cpuif.data_width - 1}:0] {slave_prefix}RDATA",
+            f"output logic [1:0] {slave_prefix}RRESP",
+        ]
+
+    def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
+        return [
+            # Write address channel
+            f"output logic {self.signal('AWVALID', child)}",
+            f"input  logic {self.signal('AWREADY', child)}",
+            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('AWADDR', child)}",
+            f"output logic [2:0] {self.signal('AWPROT', child)}",
+            # Write data channel
+            f"output logic {self.signal('WVALID', child)}",
+            f"input  logic {self.signal('WREADY', child)}",
+            f"output logic [{self.cpuif.data_width - 1}:0] {self.signal('WDATA', child)}",
+            f"output logic [{self.cpuif.data_width // 8 - 1}:0] {self.signal('WSTRB', child)}",
+            # Write response channel
+            f"input  logic {self.signal('BVALID', child)}",
+            f"output logic {self.signal('BREADY', child)}",
+            f"input  logic [1:0] {self.signal('BRESP', child)}",
+            # Read address channel
+            f"output logic {self.signal('ARVALID', child)}",
+            f"input  logic {self.signal('ARREADY', child)}",
+            f"output logic [{self.cpuif.addr_width - 1}:0] {self.signal('ARADDR', child)}",
+            f"output logic [2:0] {self.signal('ARPROT', child)}",
+            # Read data channel
+            f"input  logic {self.signal('RVALID', child)}",
+            f"output logic {self.signal('RREADY', child)}",
+            f"input  logic [{self.cpuif.data_width - 1}:0] {self.signal('RDATA', child)}",
+            f"input  logic [1:0] {self.signal('RRESP', child)}",
+        ]

src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv

@@ -15,6 +15,7 @@
                         $bits({{cpuif.signal("WDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
     end
 
+    `ifdef PEAKRDL_ASSERTIONS
     // Simple handshake sanity (one-cycle implication; relax/adjust as needed)
     assert_rd_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
         {{cpuif.signal("RVALID")}} |-> (^{{cpuif.signal("RRESP")}} !== 1'bx))
@@ -23,6 +24,7 @@
     assert_wr_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
         {{cpuif.signal("BVALID")}} |-> (^{{cpuif.signal("BRESP")}} !== 1'bx))
             else $error("BRESP must be a legal AXI response when BVALID is high");
+    `endif
 `endif
 {% endif -%}
 
@@ -53,6 +55,13 @@ assign {{cpuif.signal("BRESP")}}  = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpu
 // Fanout CPU Bus interface signals
 //--------------------------------------------------------------------------
 {{fanout|walk(cpuif=cpuif)}}
+{%- if cpuif.is_interface %}
+
+//--------------------------------------------------------------------------
+// Intermediate signals for interface array fanin
+//--------------------------------------------------------------------------
+{{fanin_intermediate|walk(cpuif=cpuif)}}
+{%- endif %}
 
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals

src/peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -7,6 +7,7 @@ from systemrdl.node import AddressableNode
 
 from ..utils import clog2, get_indexed_path, is_pow2, roundup_pow2
 from .fanin_gen import FaninGenerator
+from .fanin_intermediate_gen import FaninIntermediateGenerator
 from .fanout_gen import FanoutGenerator
 
 if TYPE_CHECKING:
@@ -24,11 +25,7 @@ class BaseCpuif:
 
     @property
     def addressable_children(self) -> list[AddressableNode]:
-        return [
+        return self.exp.ds.get_addressable_children_at_depth(unroll=self.unroll)
-            child
-            for child in self.exp.ds.top_node.children(unroll=self.unroll)
-            if isinstance(child, AddressableNode)
-        ]
 
     @property
     def addr_width(self) -> int:
@@ -97,6 +94,7 @@ class BaseCpuif:
             "ds": self.exp.ds,
             "fanout": FanoutGenerator,
             "fanin": FaninGenerator,
+            "fanin_intermediate": FaninIntermediateGenerator,
         }
 
         template = jj_env.get_template(self.template_path)
@@ -116,3 +114,24 @@ class BaseCpuif:
 
     def readback(self, node: AddressableNode | None = None) -> str:
         raise NotImplementedError
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for interface array fanin.
+
+        This method should be implemented by cpuif classes that use interfaces.
+        It returns a list of assignment strings that copy signals from interface
+        arrays to intermediate unpacked arrays using constant (genvar) indexing.
+
+        Args:
+            node: The addressable node
+            inst_name: Instance name for the intermediate signals
+            array_idx: Array index string (e.g., "[gi0][gi1]")
+            master_prefix: Master interface prefix
+            indexed_path: Indexed path to the interface element
+
+        Returns:
+            List of assignment strings
+        """
+        return []  # Default: no intermediate assignments needed

src/peakrdl_busdecoder/cpuif/fanin_gen.py

@@ -27,6 +27,17 @@ class FaninGenerator(BusDecoderListener):
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
+        should_generate = action == WalkerAction.SkipDescendants
+        if not should_generate and self._ds.max_decode_depth == 0:
+            for child in node.children():
+                if isinstance(child, AddressableNode):
+                    break
+            else:
+                should_generate = True
+
+        if not should_generate:
+            return action
+
         if node.array_dimensions:
             for i, dim in enumerate(node.array_dimensions):
                 fb = ForLoopBody(
@@ -36,18 +47,17 @@ class FaninGenerator(BusDecoderListener):
                 )
                 self._stack.append(fb)
 
-        if action == WalkerAction.Continue:
+        ifb = IfBody()
-            ifb = IfBody()
+        with ifb.cm(
-            with ifb.cm(
+            f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)} || cpuif_wr_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}"
-                f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)} || cpuif_wr_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}"
+        ) as b:
-            ) as b:
+            b += self._cpuif.fanin(node)
-                b += self._cpuif.fanin(node)
+        self._stack[-1] += ifb
-            self._stack[-1] += ifb
 
-            ifb = IfBody()
+        ifb = IfBody()
-            with ifb.cm(f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}") as b:
+        with ifb.cm(f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}") as b:
-                b += self._cpuif.readback(node)
+            b += self._cpuif.readback(node)
-            self._stack[-1] += ifb
+        self._stack[-1] += ifb
 
         return action
 

src/peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py

@@ -0,0 +1,142 @@
+"""Generator for intermediate signals needed for interface array fanin.
+
+When using SystemVerilog interface arrays, we cannot use variable indices
+in procedural blocks (like always_comb). This generator creates intermediate
+signals that copy from interface arrays using generate loops, which can then
+be safely accessed with variable indices in the fanin logic.
+"""
+
+from collections import deque
+from typing import TYPE_CHECKING
+
+from systemrdl.node import AddressableNode
+from systemrdl.walker import WalkerAction
+
+from ..body import Body, ForLoopBody
+from ..design_state import DesignState
+from ..listener import BusDecoderListener
+from ..utils import get_indexed_path
+
+if TYPE_CHECKING:
+    from .base_cpuif import BaseCpuif
+
+
+class FaninIntermediateGenerator(BusDecoderListener):
+    """Generates intermediate signals for interface array fanin."""
+
+    def __init__(self, ds: DesignState, cpuif: "BaseCpuif") -> None:
+        super().__init__(ds)
+        self._cpuif = cpuif
+        self._declarations: list[str] = []
+        self._stack: deque[Body] = deque()
+        self._stack.append(Body())
+
+    def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
+        action = super().enter_AddressableComponent(node)
+
+        # Only generate intermediates for interface arrays
+        # Check if cpuif has is_interface attribute (some implementations don't)
+        is_interface = getattr(self._cpuif, "is_interface", False)
+        if not is_interface or not node.array_dimensions:
+            return action
+
+        # Generate intermediate signal declarations
+        self._generate_intermediate_declarations(node)
+
+        # Generate assignment logic using generate loops
+        if node.array_dimensions:
+            for i, dim in enumerate(node.array_dimensions):
+                fb = ForLoopBody(
+                    "genvar",
+                    f"gi{i}",
+                    dim,
+                )
+                self._stack.append(fb)
+
+        # Generate assignments from interface array to intermediates
+        self._stack[-1] += self._generate_intermediate_assignments(node)
+
+        return action
+
+    def exit_AddressableComponent(self, node: AddressableNode) -> None:
+        is_interface = getattr(self._cpuif, "is_interface", False)
+        if is_interface and node.array_dimensions:
+            for _ in node.array_dimensions:
+                b = self._stack.pop()
+                if not b:
+                    continue
+                self._stack[-1] += b
+
+        super().exit_AddressableComponent(node)
+
+    def _generate_intermediate_declarations(self, node: AddressableNode) -> None:
+        """Generate intermediate signal declarations for a node."""
+        inst_name = node.inst_name
+
+        # Array dimensions should be checked before calling this function
+        if not node.array_dimensions:
+            return
+
+        # Calculate total array size
+        array_size = 1
+        for dim in node.array_dimensions:
+            array_size *= dim
+
+        # Create array dimension string
+        array_str = "".join(f"[{dim}]" for dim in node.array_dimensions)
+
+        # Generate declarations for each fanin signal
+        # For APB3/4: PREADY, PSLVERR, PRDATA
+        # These are the signals read in fanin
+        self._declarations.append(f"logic {inst_name}_fanin_ready{array_str};")
+        self._declarations.append(f"logic {inst_name}_fanin_err{array_str};")
+        self._declarations.append(
+            f"logic [{self._cpuif.data_width - 1}:0] {inst_name}_fanin_data{array_str};"
+        )
+
+    def _generate_intermediate_assignments(self, node: AddressableNode) -> str:
+        """Generate assignments from interface array to intermediate signals."""
+        inst_name = node.inst_name
+        indexed_path = get_indexed_path(node.parent, node, "gi", skip_kw_filter=True)
+
+        # Get master prefix - use getattr to avoid type errors
+        interface = getattr(self._cpuif, "_interface", None)
+        if interface is None:
+            return ""
+        master_prefix = interface.get_master_prefix()
+
+        # Array dimensions should be checked before calling this function
+        if not node.array_dimensions:
+            return ""
+
+        # Create indexed signal names for left-hand side
+        array_idx = "".join(f"[gi{i}]" for i in range(len(node.array_dimensions)))
+
+        # Delegate to cpuif to get the appropriate assignments for this interface type
+        assignments = self._cpuif.fanin_intermediate_assignments(
+            node, inst_name, array_idx, master_prefix, indexed_path
+        )
+
+        return "\n".join(assignments)
+
+    def get_declarations(self) -> str:
+        """Get all intermediate signal declarations."""
+        if not self._declarations:
+            return ""
+        return "\n".join(self._declarations)
+
+    def __str__(self) -> str:
+        """Get all intermediate signal declarations and assignments."""
+        if not self._declarations:
+            return ""
+
+        # Output declarations first
+        output = "\n".join(self._declarations)
+        output += "\n\n"
+
+        # Then output assignments
+        body_str = "\n".join(map(str, self._stack))
+        if body_str and body_str.strip():
+            output += body_str
+
+        return output

src/peakrdl_busdecoder/cpuif/fanout_gen.py

@@ -23,6 +23,17 @@ class FanoutGenerator(BusDecoderListener):
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
+        should_generate = action == WalkerAction.SkipDescendants
+        if not should_generate and self._ds.max_decode_depth == 0:
+            for child in node.children():
+                if isinstance(child, AddressableNode):
+                    break
+            else:
+                should_generate = True
+
+        if not should_generate:
+            return action
+
         if node.array_dimensions:
             for i, dim in enumerate(node.array_dimensions):
                 fb = ForLoopBody(
@@ -32,8 +43,7 @@ class FanoutGenerator(BusDecoderListener):
                 )
                 self._stack.append(fb)
 
-        if action == WalkerAction.Continue:
+        self._stack[-1] += self._cpuif.fanout(node)
-            self._stack[-1] += self._cpuif.fanout(node)
 
         return action
 

src/peakrdl_busdecoder/cpuif/interface.py

@@ -0,0 +1,202 @@
+"""Interface abstraction for handling flat and non-flat signal declarations."""
+
+import re
+from abc import ABC, abstractmethod
+from typing import TYPE_CHECKING
+
+from systemrdl.node import AddressableNode
+
+from ..utils import get_indexed_path
+
+if TYPE_CHECKING:
+    from .base_cpuif import BaseCpuif
+
+
+class Interface(ABC):
+    """Abstract base class for interface signal handling."""
+
+    def __init__(self, cpuif: "BaseCpuif") -> None:
+        self.cpuif = cpuif
+
+    @property
+    @abstractmethod
+    def is_interface(self) -> bool:
+        """Whether this uses SystemVerilog interfaces."""
+        ...
+
+    @abstractmethod
+    def get_port_declaration(self, slave_name: str, master_prefix: str) -> str:
+        """
+        Generate port declarations for the interface.
+
+        Args:
+            slave_name: Name of the slave interface/signal prefix
+            master_prefix: Prefix for master interfaces/signals
+
+        Returns:
+            Port declarations as a string
+        """
+        ...
+
+    @abstractmethod
+    def signal(
+        self,
+        signal: str,
+        node: AddressableNode | None = None,
+        indexer: str | int | None = None,
+    ) -> str:
+        """
+        Generate signal reference.
+
+        Args:
+            signal: Signal name
+            node: Optional addressable node for master signals
+            indexer: Optional indexer for arrays.
+                     For SVInterface: str like "i" or "gi" for loop indices
+                     For FlatInterface: str or int for array subscript
+
+        Returns:
+            Signal reference as a string
+        """
+        ...
+
+
+class SVInterface(Interface):
+    """SystemVerilog interface-based signal handling."""
+
+    slave_modport_name = "slave"
+    master_modport_name = "master"
+
+    @property
+    def is_interface(self) -> bool:
+        return True
+
+    def get_port_declaration(self, slave_name: str, master_prefix: str) -> str:
+        """Generate SystemVerilog interface port declarations."""
+        slave_ports: list[str] = [f"{self.get_interface_type()}.{self.slave_modport_name} {slave_name}"]
+        master_ports: list[str] = []
+
+        for child in self.cpuif.addressable_children:
+            base = f"{self.get_interface_type()}.{self.master_modport_name} {master_prefix}{child.inst_name}"
+
+            # When unrolled, current_idx is set - append it to the name
+            if child.current_idx is not None:
+                base = f"{base}_{'_'.join(map(str, child.current_idx))}"
+
+            # Only add array dimensions if this should be treated as an array
+            if self.cpuif.check_is_array(child):
+                assert child.array_dimensions is not None
+                base = f"{base} {''.join(f'[{dim}]' for dim in child.array_dimensions)}"
+
+            master_ports.append(base)
+
+        return ",\n".join(slave_ports + master_ports)
+
+    def signal(
+        self,
+        signal: str,
+        node: AddressableNode | None = None,
+        indexer: str | int | None = None,
+    ) -> str:
+        """Generate SystemVerilog interface signal reference."""
+
+        # SVInterface only supports string indexers (loop variable names like "i", "gi")
+        if indexer is not None and not isinstance(indexer, str):
+            raise TypeError(f"SVInterface.signal() requires string indexer, got {type(indexer).__name__}")
+
+        if node is None or indexer is None:
+            # Node is none, so this is a slave signal
+            slave_name = self.get_slave_name()
+            return f"{slave_name}.{signal}"
+
+        # Master signal
+        master_prefix = self.get_master_prefix()
+        return f"{master_prefix}{get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)}.{signal}"
+
+    @abstractmethod
+    def get_interface_type(self) -> str:
+        """Get the SystemVerilog interface type name."""
+        ...
+
+    @abstractmethod
+    def get_slave_name(self) -> str:
+        """Get the slave interface instance name."""
+        ...
+
+    @abstractmethod
+    def get_master_prefix(self) -> str:
+        """Get the master interface name prefix."""
+        ...
+
+
+class FlatInterface(Interface):
+    """Flat signal-based interface handling."""
+
+    @property
+    def is_interface(self) -> bool:
+        return False
+
+    def get_port_declaration(self, slave_name: str, master_prefix: str) -> str:
+        """Generate flat port declarations."""
+        slave_ports = self._get_slave_port_declarations(slave_name)
+        master_ports: list[str] = []
+
+        for child in self.cpuif.addressable_children:
+            master_ports.extend(self._get_master_port_declarations(child, master_prefix))
+
+        return ",\n".join(slave_ports + master_ports)
+
+    def signal(
+        self,
+        signal: str,
+        node: AddressableNode | None = None,
+        indexer: str | int | None = None,
+    ) -> str:
+        """Generate flat signal reference."""
+        if node is None:
+            # Node is none, so this is a slave signal
+            slave_prefix = self.get_slave_prefix()
+            return f"{slave_prefix}{signal}"
+
+        # Master signal
+        master_prefix = self.get_master_prefix()
+        base = f"{master_prefix}{node.inst_name}"
+
+        if not self.cpuif.check_is_array(node):
+            # Not an array or an unrolled element
+            if node.current_idx is not None:
+                # This is a specific instance of an unrolled array
+                return f"{base}_{signal}_{'_'.join(map(str, node.current_idx))}"
+            return f"{base}_{signal}"
+
+        # Is an array
+        if indexer is not None:
+            if isinstance(indexer, str):
+                indexed_path = get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)
+                pattern = r"\[.*?\]"
+                indexes = re.findall(pattern, indexed_path)
+
+                return f"{base}_{signal}{''.join(indexes)}"
+
+            return f"{base}_{signal}[{indexer}]"
+        return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
+
+    @abstractmethod
+    def _get_slave_port_declarations(self, slave_prefix: str) -> list[str]:
+        """Get slave port declarations."""
+        ...
+
+    @abstractmethod
+    def _get_master_port_declarations(self, child: AddressableNode, master_prefix: str) -> list[str]:
+        """Get master port declarations for a child node."""
+        ...
+
+    @abstractmethod
+    def get_slave_prefix(self) -> str:
+        """Get the slave signal name prefix."""
+        ...
+
+    @abstractmethod
+    def get_master_prefix(self) -> str:
+        """Get the master signal name prefix."""
+        ...

src/peakrdl_busdecoder/cpuif/taxi_apb/__init__.py

@@ -0,0 +1,3 @@
+from .taxi_apb_cpuif import TaxiAPBCpuif
+
+__all__ = ["TaxiAPBCpuif"]

src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_cpuif.py

@@ -0,0 +1,99 @@
+from typing import TYPE_CHECKING, overload
+
+from systemrdl.node import AddressableNode
+
+from ...utils import get_indexed_path
+from ..base_cpuif import BaseCpuif
+from .taxi_apb_interface import TaxiAPBSVInterface
+
+if TYPE_CHECKING:
+    from ...exporter import BusDecoderExporter
+
+
+class TaxiAPBCpuif(BaseCpuif):
+    template_path = "taxi_apb_tmpl.sv"
+
+    def __init__(self, exp: "BusDecoderExporter") -> None:
+        super().__init__(exp)
+        self._interface = TaxiAPBSVInterface(self)
+        self._interface.master_modport_name = "mst"
+        self._interface.slave_modport_name = "slv"
+
+    @property
+    def is_interface(self) -> bool:
+        return self._interface.is_interface
+
+    @property
+    def port_declaration(self) -> str:
+        """Returns the port declaration for the APB4 interface."""
+        return self._interface.get_port_declaration("s_apb", "m_apb_")
+
+    @overload
+    def signal(self, signal: str, node: None = None, indexer: None = None) -> str: ...
+    @overload
+    def signal(self, signal: str, node: AddressableNode, indexer: str) -> str: ...
+    def signal(self, signal: str, node: AddressableNode | None = None, indexer: str | None = None) -> str:
+        return self._interface.signal(signal, node, indexer)
+
+    def fanout(self, node: AddressableNode) -> str:
+        fanout: dict[str, str] = {}
+        fanout[self.signal("psel", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        )
+        fanout[self.signal("penable", node, "gi")] = self.signal("penable")
+        fanout[self.signal("pwrite", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
+        )
+        fanout[self.signal("paddr", node, "gi")] = self.signal("paddr")
+        fanout[self.signal("pprot", node, "gi")] = self.signal("pprot")
+        fanout[self.signal("pwdata", node, "gi")] = "cpuif_wr_data"
+        fanout[self.signal("pstrb", node, "gi")] = "cpuif_wr_byte_en"
+        # no user?
+
+        return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
+
+    def fanin(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
+        else:
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+            else:
+                fanin["cpuif_rd_ack"] = self.signal("pready", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("pslverr", node, "i")
+
+        # no user?
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def readback(self, node: AddressableNode | None = None) -> str:
+        fanin: dict[str, str] = {}
+        if node is None:
+            fanin["cpuif_rd_data"] = "'0"
+        else:
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
+            else:
+                fanin["cpuif_rd_data"] = self.signal("prdata", node, "i")
+
+        return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for APB4 interface arrays."""
+        return [
+            f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.pready;",
+            f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.pslverr;",
+            f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.prdata;",
+        ]

src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_interface.py

@@ -0,0 +1,16 @@
+"""Taxi APB-specific interface implementations."""
+
+from ..interface import SVInterface
+
+
+class TaxiAPBSVInterface(SVInterface):
+    """Taxi APB SystemVerilog interface."""
+
+    def get_interface_type(self) -> str:
+        return "taxi_apb_if"
+
+    def get_slave_name(self) -> str:
+        return "s_apb"
+
+    def get_master_prefix(self) -> str:
+        return "m_apb_"

src/peakrdl_busdecoder/cpuif/taxi_apb/taxi_apb_tmpl.sv

@@ -0,0 +1,45 @@
+{%- if cpuif.is_interface %}
+`ifndef SYNTHESIS
+    initial begin
+        assert_bad_addr_width: assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
+        assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
+    end
+    `ifdef PEAKRDL_ASSERTIONS
+    assert_wr_sel: assert property (@(posedge {{cpuif.signal("PCLK")}}) {{cpuif.signal("psel")}} && {{cpuif.signal("pwrite")}} |-> ##1 ({{cpuif.signal("pready")}} || {{cpuif.signal("pslverr")}}))
+        else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+    `endif
+`endif
+{%- endif %}
+
+assign cpuif_req   = {{cpuif.signal("psel")}};
+assign cpuif_wr_en = {{cpuif.signal("pwrite")}};
+assign cpuif_rd_en = !{{cpuif.signal("pwrite")}};
+
+assign cpuif_wr_addr = {{cpuif.signal("paddr")}};
+assign cpuif_rd_addr = {{cpuif.signal("paddr")}};
+
+assign cpuif_wr_data = {{cpuif.signal("pwdata")}};
+assign cpuif_wr_byte_en = {{cpuif.signal("pstrb")}};
+
+assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
+assign {{cpuif.signal("pready")}} = cpuif_rd_ack;
+assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+
+//--------------------------------------------------------------------------
+// Fanout CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanout|walk(cpuif=cpuif)}}
+{%- if cpuif.is_interface %}
+
+//--------------------------------------------------------------------------
+// Intermediate signals for interface array fanin
+//--------------------------------------------------------------------------
+{{fanin_intermediate|walk(cpuif=cpuif)}}
+{%- endif %}
+
+//--------------------------------------------------------------------------
+// Fanin CPU Bus interface signals
+//--------------------------------------------------------------------------
+{{fanin|walk(cpuif=cpuif)}}

src/peakrdl_busdecoder/decode_logic_gen.py

@@ -63,11 +63,18 @@ class DecodeLogicGenerator(BusDecoderListener):
             l_bound_comp.append(f"({addr_width}'(i{i})*{SVInt(stride, addr_width)})")
             u_bound_comp.append(f"({addr_width}'(i{i})*{SVInt(stride, addr_width)})")
 
-        # Generate Conditions
+        lower_expr = f"{self._flavor.cpuif_address} >= ({'+'.join(l_bound_comp)})"
-        return [
+        upper_expr = f"{self._flavor.cpuif_address} < ({'+'.join(u_bound_comp)})"
-            f"{self._flavor.cpuif_address} >= ({'+'.join(l_bound_comp)})",
+
-            f"{self._flavor.cpuif_address} < ({'+'.join(u_bound_comp)})",
+        predicates: list[str] = []
-        ]
+        # Avoid generating a redundant >= 0 comparison, which triggers Verilator warnings.
+        if not (l_bound.value == 0 and len(l_bound_comp) == 1):
+            predicates.append(lower_expr)
+        # Avoid generating a redundant full-width < max comparison, which triggers Verilator warnings.
+        if not (u_bound.value == (1 << addr_width) and len(u_bound_comp) == 1):
+            predicates.append(upper_expr)
+
+        return predicates
 
     def cpuif_prot_predicate(self, node: AddressableNode) -> list[str]:
         if self._flavor == DecodeLogicFlavor.READ:
@@ -80,6 +87,20 @@ class DecodeLogicGenerator(BusDecoderListener):
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
+        should_decode = action == WalkerAction.SkipDescendants
+
+        if not should_decode and self._ds.max_decode_depth == 0:
+            # When decoding all levels, treat leaf registers as decode boundary
+            for child in node.children():
+                if isinstance(child, AddressableNode):
+                    break
+            else:
+                should_decode = True
+
+        # Only generate select logic if we're at the decode boundary
+        if not should_decode:
+            return action
+
         conditions: list[str] = []
         conditions.extend(self.cpuif_addr_predicate(node))
         conditions.extend(self.cpuif_prot_predicate(node))
@@ -141,6 +162,8 @@ class DecodeLogicGenerator(BusDecoderListener):
     def __str__(self) -> str:
         body = self._decode_stack[-1]
         if isinstance(body, IfBody):
+            if len(body) == 0:
+                return f"{self._flavor.cpuif_select}.cpuif_err = 1'b1;"
             with body.cm(...) as b:
                 b += f"{self._flavor.cpuif_select}.cpuif_err = 1'b1;"
 

src/peakrdl_busdecoder/design_state.py

@@ -1,6 +1,6 @@
 from typing import TypedDict
 
-from systemrdl.node import AddrmapNode
+from systemrdl.node import AddressableNode, AddrmapNode
 from systemrdl.rdltypes.user_enum import UserEnum
 
 from .design_scanner import DesignScanner
@@ -14,6 +14,7 @@ class DesignStateKwargs(TypedDict, total=False):
     package_name: str
     address_width: int
     cpuif_unroll: bool
+    max_decode_depth: int
 
 
 class DesignState:
@@ -35,6 +36,7 @@ class DesignState:
         user_addr_width: int | None = kwargs.pop("address_width", None)
 
         self.cpuif_unroll: bool = kwargs.pop("cpuif_unroll", False)
+        self.max_decode_depth: int = kwargs.pop("max_decode_depth", 1)
 
         # ------------------------
         # Info about the design
@@ -70,3 +72,56 @@ class DesignState:
         if user_addr_width < self.addr_width:
             msg.fatal(f"User-specified address width shall be greater than or equal to {self.addr_width}.")
         self.addr_width = user_addr_width
+
+    def get_addressable_children_at_depth(self, unroll: bool = False) -> list[AddressableNode]:
+        """
+        Get addressable children at the decode boundary based on max_decode_depth.
+
+        max_decode_depth semantics:
+        - 0: decode all levels (return leaf registers)
+        - 1: decode only top level (return children at depth 1)
+        - 2: decode top + 1 level (return children at depth 2)
+        - N: decode down to depth N (return children at depth N)
+
+        Args:
+            unroll: Whether to unroll arrayed nodes
+
+        Returns:
+            List of addressable nodes at the decode boundary
+        """
+        from systemrdl.node import RegNode
+
+        def collect_nodes(node: AddressableNode, current_depth: int) -> list[AddressableNode]:
+            """Recursively collect nodes at the decode boundary."""
+            result: list[AddressableNode] = []
+
+            # For depth 0, collect all leaf registers
+            if self.max_decode_depth == 0:
+                # If this is a register, it's a leaf
+                if isinstance(node, RegNode):
+                    result.append(node)
+                else:
+                    # Recurse into children
+                    for child in node.children(unroll=unroll):
+                        if isinstance(child, AddressableNode):
+                            result.extend(collect_nodes(child, current_depth + 1))
+            else:
+                # For depth N, collect children at depth N
+                if current_depth == self.max_decode_depth:
+                    # We're at the decode boundary - return this node
+                    result.append(node)
+                elif current_depth < self.max_decode_depth:
+                    # We haven't reached the boundary yet - recurse
+                    for child in node.children(unroll=unroll):
+                        if isinstance(child, AddressableNode):
+                            result.extend(collect_nodes(child, current_depth + 1))
+
+            return result
+
+        # Start collecting from top node's children
+        nodes: list[AddressableNode] = []
+        for child in self.top_node.children(unroll=unroll):
+            if isinstance(child, AddressableNode):
+                nodes.extend(collect_nodes(child, 1))
+
+        return nodes

src/peakrdl_busdecoder/exporter.py

@@ -17,6 +17,7 @@ from .identifier_filter import kw_filter as kwf
 from .listener import BusDecoderListener
 from .struct_gen import StructGenerator
 from .sv_int import SVInt
+from .utils import clog2
 from .validate_design import DesignValidator
 
 
@@ -27,6 +28,7 @@ class ExporterKwargs(TypedDict, total=False):
     address_width: int
     cpuif_unroll: bool
     reuse_hwif_typedefs: bool
+    max_decode_depth: int
 
 
 if TYPE_CHECKING:
@@ -59,6 +61,7 @@ class BusDecoderExporter:
         )
         self.jj_env.filters["kwf"] = kwf  # type: ignore
         self.jj_env.filters["walk"] = self.walk  # type: ignore
+        self.jj_env.filters["clog2"] = clog2  # type: ignore
 
     def export(self, node: RootNode | AddrmapNode, output_dir: str, **kwargs: Unpack[ExporterKwargs]) -> None:
         """
@@ -84,6 +87,11 @@ class BusDecoderExporter:
         cpuif_unroll: bool
             Unroll arrayed addressable nodes into separate instances in the CPU
             interface. By default, arrayed nodes are kept as arrays.
+        max_decode_depth: int
+            Maximum depth for address decoder to descend into nested addressable
+            components. A value of 0 decodes all levels (infinite depth). A value
+            of 1 decodes only top-level children. A value of 2 decodes top-level
+            and one level deeper, etc. By default, the decoder descends 1 level deep.
         """
         # If it is the root node, skip to top addrmap
         if isinstance(node, RootNode):

src/peakrdl_busdecoder/listener.py

@@ -1,6 +1,6 @@
 from collections import deque
 
-from systemrdl.node import AddressableNode
+from systemrdl.node import AddressableNode, RegNode
 from systemrdl.walker import RDLListener, WalkerAction
 
 from .design_state import DesignState
@@ -12,15 +12,44 @@ class BusDecoderListener(RDLListener):
         self._ds = ds
         self._depth = 0
 
+    def should_skip_node(self, node: AddressableNode) -> bool:
+        """Check if this node should be skipped (not decoded)."""
+        # Check if current depth exceeds max depth
+        # max_decode_depth semantics:
+        # - 0 means decode all levels (infinite)
+        # - 1 means decode only top level (depth 0)
+        # - 2 means decode top + 1 level (depth 0 and 1)
+        # - N means decode down to depth N-1
+        if self._ds.max_decode_depth > 0 and self._depth >= self._ds.max_decode_depth:
+            return True
+
+        # Check if this node only contains external addressable children
+        if node != self._ds.top_node and not isinstance(node, RegNode):
+            if any(isinstance(c, AddressableNode) for c in node.children()) and all(
+                c.external for c in node.children() if isinstance(c, AddressableNode)
+            ):
+                return True
+
+        return False
+
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         if node.array_dimensions:
             assert node.array_stride is not None, "Array stride should be defined for arrayed components"
-            self._array_stride_stack.extend(node.array_dimensions)
+            current_stride = node.array_stride
+            self._array_stride_stack.append(current_stride)
+
+            # Work backwards from rightmost to leftmost dimension (fastest to slowest changing)
+            # Each dimension's stride is the product of its size and the previous dimension's stride
+            for dim in node.array_dimensions[-1:0:-1]:
+                current_stride = current_stride * dim
+                self._array_stride_stack.appendleft(current_stride)
 
         self._depth += 1
 
-        if self._depth > 1:
+        # Check if we should skip this node's descendants
+        if self.should_skip_node(node):
             return WalkerAction.SkipDescendants
+
         return WalkerAction.Continue
 
     def exit_AddressableComponent(self, node: AddressableNode) -> None:

src/peakrdl_busdecoder/module_tmpl.sv

@@ -1,13 +1,12 @@
-
 //==========================================================
 //  Module: {{ds.module_name}}
 //  Description: CPU Interface Bus Decoder
-//  Author: PeakRDL-busdecoder
+//  Author: PeakRDL-BusDecoder
 //  License: LGPL-3.0
 //  Date: {{current_date}}
 //  Version: {{version}}
 //  Links:
-//    - https://github.com/arnavsacheti/PeakRDL-busdecoder
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
 //==========================================================
 
 
@@ -17,7 +16,6 @@ module {{ds.module_name}}
 ) {%- endif %} (
     {{cpuif.port_declaration|indent(4)}}
 );
-
     //--------------------------------------------------------------------------
     // CPU Bus interface logic
     //--------------------------------------------------------------------------
@@ -46,14 +44,14 @@ module {{ds.module_name}}
     //--------------------------------------------------------------------------
     // Slave <-> Internal CPUIF <-> Master
     //--------------------------------------------------------------------------
-    {{-cpuif.get_implementation()|indent(4)}}
+    {{cpuif.get_implementation()|indent(4)}}
 
     //--------------------------------------------------------------------------
     // Write Address Decoder
     //--------------------------------------------------------------------------
     always_comb begin
         // Default all write select signals to 0
-        cpuif_wr_sel = '0;
+        cpuif_wr_sel = '{default: '0};
 
         if (cpuif_req && cpuif_wr_en) begin
             // A write request is pending
@@ -68,7 +66,7 @@ module {{ds.module_name}}
     //--------------------------------------------------------------------------
     always_comb begin
         // Default all read select signals to 0
-        cpuif_rd_sel = '0;
+        cpuif_rd_sel = '{default: '0};
 
         if (cpuif_req && cpuif_rd_en) begin
             // A read request is pending

src/peakrdl_busdecoder/package_tmpl.sv

@@ -1,10 +1,21 @@
-// Generated by PeakRDL-busdecoder - A free and open-source SystemVerilog generator
+//==========================================================
-//  https://github.com/arnavsacheti/PeakRDL-busdecoder
+//  Package: {{ds.package_name}}
+//  Description: CPU Interface Bus Decoder Package
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: {{current_date}}
+//  Version: {{version}}
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
 
 package {{ds.package_name}};
-
     localparam {{ds.module_name.upper()}}_DATA_WIDTH = {{ds.cpuif_data_width}};
     localparam {{ds.module_name.upper()}}_MIN_ADDR_WIDTH = {{ds.addr_width}};
     localparam {{ds.module_name.upper()}}_SIZE = {{SVInt(ds.top_node.size)}};
+{%- for child in cpuif.addressable_children %}
+    localparam {{ds.module_name.upper()}}_{{child.inst_name.upper()}}_ADDR_WIDTH = {{child.size|clog2}};
+{%- endfor %}
 endpackage
 {# (eof newline anchor) #}

src/peakrdl_busdecoder/struct_gen.py

@@ -3,7 +3,7 @@ from collections import deque
 from systemrdl.node import AddressableNode
 from systemrdl.walker import WalkerAction
 
-from .body import Body, StructBody
+from .body import StructBody
 from .design_state import DesignState
 from .identifier_filter import kw_filter as kwf
 from .listener import BusDecoderListener
@@ -16,42 +16,53 @@ class StructGenerator(BusDecoderListener):
     ) -> None:
         super().__init__(ds)
 
-        self._stack: deque[Body] = deque()
+        self._stack: list[StructBody] = [StructBody("cpuif_sel_t", True, False)]
-        self._stack.append(StructBody("cpuif_sel_t", True, True))
+        self._struct_defs: list[StructBody] = []
+        self._created_struct_stack: deque[bool] = deque()  # Track if we created a struct for each node
 
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
-        self._skip = False
+        skip = action == WalkerAction.SkipDescendants
-        if action == WalkerAction.SkipDescendants:
-            self._skip = True
 
-        if node.children():
+        # Only create nested struct if we're not skipping and node has addressable children
+        has_addressable_children = any(isinstance(child, AddressableNode) for child in node.children())
+        if has_addressable_children and not skip:
             # Push new body onto stack
-            body = StructBody(f"cpuif_sel_{node.inst_name}_t", True, True)
+            body = StructBody(f"cpuif_sel_{node.inst_name}_t", True, False)
             self._stack.append(body)
+            self._created_struct_stack.append(True)
+        else:
+            self._created_struct_stack.append(False)
 
         return action
 
     def exit_AddressableComponent(self, node: AddressableNode) -> None:
         type = "logic"
 
-        if node.children():
+        # Pop the created_struct flag
+        created_struct = self._created_struct_stack.pop()
+
+        # Only pop struct body if we created one
+        if created_struct:
             body = self._stack.pop()
-            if body and isinstance(body, StructBody) and not self._skip:
+            if body:
-                self._stack.appendleft(body)
+                self._struct_defs.append(body)
                 type = body.name
 
         name = kwf(node.inst_name)
 
         if node.array_dimensions:
             for dim in node.array_dimensions:
-                name = f"[{dim - 1}:0]{name}"
+                name = f"{name}[{dim}]"
 
         self._stack[-1] += f"{type} {name};"
 
         super().exit_AddressableComponent(node)
 
     def __str__(self) -> str:
-        self._stack[-1] += "logic cpuif_err;"
+        if "logic cpuif_err;" not in self._stack[-1].lines:
-        return "\n".join(map(str, self._stack))
+            self._stack[-1] += "logic cpuif_err;"
+        bodies = [str(body) for body in self._struct_defs]
+        bodies.append(str(self._stack[-1]))
+        return "\n".join(bodies)

src/peakrdl_busdecoder/sv_int.py

@@ -1,3 +1,6 @@
+from typing import Literal
+
+
 class SVInt:
     def __init__(self, value: int, width: int | None = None) -> None:
         self.value = value
@@ -19,3 +22,27 @@ class SVInt:
             return SVInt(self.value + other.value, max(self.width, other.width))
         else:
             return SVInt(self.value + other.value, None)
+
+    def __sub__(self, other: "SVInt") -> "SVInt":
+        if self.width is not None and other.width is not None:
+            return SVInt(self.value - other.value, max(self.width, other.width))
+        else:
+            return SVInt(self.value - other.value, None)
+
+    def __len__(self) -> int:
+        if self.width is not None:
+            return self.width
+        else:
+            return self.value.bit_length()
+
+    def to_bytes(self, byteorder: Literal["little", "big"] = "little") -> bytes:
+        byte_length = (self.value.bit_length() + 7) // 8
+        return self.value.to_bytes(byte_length, byteorder)
+
+    def __eq__(self, other: object) -> bool:
+        if not isinstance(other, SVInt):
+            return NotImplemented
+        return self.value == other.value and self.width == other.width
+
+    def __hash__(self) -> int:
+        return hash((self.value, self.width))

tests/README.md

@@ -1,19 +1,27 @@
-# Unit tests
+# Tests
 
-The bus decoder exporter now ships with a small unit test suite built around
+The bus decoder exporter includes comprehensive test suites to validate both the
-`pytest`. The tests exercise the Python implementation directly and use the
+Python implementation and the generated SystemVerilog RTL.
-[`systemrdl-compiler`](https://github.com/SystemRDL/systemrdl-compiler)
+
+## Unit Tests
+
+The unit test suite is built around `pytest` and exercises the Python implementation
+directly using the [`systemrdl-compiler`](https://github.com/SystemRDL/systemrdl-compiler)
 package to elaborate inline SystemRDL snippets.
 
-## Install dependencies
+### Install dependencies
 
 Create an isolated environment if desired and install the minimal requirements:
 
 ```bash
-python -m pip install -r tests/requirements.txt
+# Using uv (recommended)
+uv sync --group test
+
+# Or using pip
+python -m pip install -e . parameterized pytest pytest-cov pytest-xdist
 ```
 
-## Running the suite
+### Running the suite
 
 Invoke `pytest` from the repository root (or the `tests` directory) and point it
 at the unit tests:
@@ -25,3 +33,67 @@ pytest tests/unit
 Pytest will automatically discover tests that follow the `test_*.py` naming
 pattern and can make use of the `compile_rdl` fixture defined in
 `tests/unit/conftest.py` to compile inline SystemRDL sources.
+
+## Cocotb Integration Tests
+
+The cocotb test suite validates the functionality of generated SystemVerilog RTL
+through simulation. These tests generate bus decoders for different CPU interfaces
+(APB3, APB4, AXI4-Lite) and verify that read/write operations work correctly.
+
+### Install dependencies
+
+```bash
+# Install with cocotb support using uv (recommended)
+uv sync --group test
+
+# Or using pip
+python -m pip install -e . parameterized pytest pytest-cov pytest-xdist cocotb cocotb-bus
+
+# Install HDL simulator (choose one)
+apt-get install iverilog  # Icarus Verilog
+apt-get install verilator # Verilator
+```
+
+### Running the tests
+
+#### Integration tests (no simulator required)
+
+These tests validate code generation without requiring an HDL simulator:
+
+```bash
+pytest tests/cocotb/testbenches/test_integration.py -v
+```
+
+#### Example code generation
+
+Run examples to see generated code for different configurations:
+
+```bash
+python tests/cocotb/examples.py
+```
+
+#### Simulation layout
+
+Simulation-oriented tests are grouped by CPU interface under
+`tests/cocotb/<cpuif>/<group>/`. For example, the APB4 smoke test lives in
+`tests/cocotb/apb4/smoke/` alongside its pytest runner module. Each runner
+compiles the appropriate SystemRDL design, adds the interface wrapper from
+`hdl-src/`, and invokes cocotb via Verilator.
+
+#### Full simulation tests (requires simulator)
+
+To execute the smoke tests for every supported interface:
+
+```bash
+pytest tests/cocotb/*/smoke/test_runner.py -v
+```
+
+To target a single interface, point pytest at that runner module:
+
+```bash
+pytest tests/cocotb/apb3/smoke/test_runner.py -v
+pytest tests/cocotb/apb4/smoke/test_runner.py -v
+pytest tests/cocotb/axi4lite/smoke/test_runner.py -v
+```
+
+For more information about cocotb tests, see [`tests/cocotb/README.md`](cocotb/README.md).

tests/body/test_body.py

@@ -0,0 +1,50 @@
+
+from peakrdl_busdecoder.body import Body
+
+
+class TestBody:
+    """Test the base Body class."""
+
+    def test_empty_body(self) -> None:
+        """Test empty body returns empty string."""
+        body = Body()
+        assert str(body) == ""
+        assert not body  # Should be falsy when empty
+
+    def test_add_single_line(self) -> None:
+        """Test adding a single line to body."""
+        body = Body()
+        body += "line1"
+        assert str(body) == "line1"
+        assert body  # Should be truthy when not empty
+
+    def test_add_multiple_lines(self) -> None:
+        """Test adding multiple lines to body."""
+        body = Body()
+        body += "line1"
+        body += "line2"
+        body += "line3"
+        expected = "line1\nline2\nline3"
+        assert str(body) == expected
+
+    def test_add_returns_self(self) -> None:
+        """Test that add operation returns self for chaining."""
+        body = Body()
+        body += "line1"
+        body += "line2"
+        # Chaining works because += returns self
+        assert len(body.lines) == 2
+
+    def test_add_nested_body(self) -> None:
+        """Test adding another body as a line."""
+        outer = Body()
+        inner = Body()
+        inner += "inner1"
+        inner += "inner2"
+        outer += "outer1"
+        outer += inner
+        outer += "outer2"
+        expected = "outer1\ninner1\ninner2\nouter2"
+        assert str(outer) == expected
+
+

tests/body/test_combinational_body.py

@@ -0,0 +1,39 @@
+from peakrdl_busdecoder.body import CombinationalBody, IfBody
+
+
+class TestCombinationalBody:
+    """Test the CombinationalBody class."""
+
+    def test_simple_combinational_block(self) -> None:
+        """Test simple combinational block."""
+        body = CombinationalBody()
+        body += "assign1 = value1;"
+        body += "assign2 = value2;"
+
+        result = str(body)
+        assert "always_comb" in result
+        assert "begin" in result
+        assert "assign1 = value1;" in result
+        assert "assign2 = value2;" in result
+        assert "end" in result
+
+    def test_empty_combinational_block(self) -> None:
+        """Test empty combinational block."""
+        body = CombinationalBody()
+        result = str(body)
+        assert "always_comb" in result
+        assert "begin" in result
+        assert "end" in result
+
+    def test_combinational_with_if_statement(self) -> None:
+        """Test combinational block with if statement."""
+        cb = CombinationalBody()
+        ifb = IfBody()
+        with ifb.cm("condition") as b:
+            b += "assignment = value;"
+        cb += ifb
+
+        result = str(cb)
+        assert "always_comb" in result
+        assert "if (condition)" in result
+        assert "assignment = value;" in result

tests/body/test_for_loop_body.py

@@ -0,0 +1,46 @@
+from peakrdl_busdecoder.body import ForLoopBody
+
+
+class TestForLoopBody:
+    """Test the ForLoopBody class."""
+
+    def test_genvar_for_loop(self) -> None:
+        """Test genvar-style for loop."""
+        body = ForLoopBody("genvar", "i", 4)
+        body += "statement1;"
+        body += "statement2;"
+
+        result = str(body)
+        assert "for (genvar i = 0; i < 4; i++)" in result
+        assert "statement1;" in result
+        assert "statement2;" in result
+        assert "end" in result
+
+    def test_int_for_loop(self) -> None:
+        """Test int-style for loop."""
+        body = ForLoopBody("int", "j", 8)
+        body += "assignment = value;"
+
+        result = str(body)
+        assert "for (int j = 0; j < 8; j++)" in result
+        assert "assignment = value;" in result
+        assert "end" in result
+
+    def test_empty_for_loop(self) -> None:
+        """Test empty for loop."""
+        body = ForLoopBody("genvar", "k", 2)
+        result = str(body)
+        # Empty for loop should still have structure
+        assert "for (genvar k = 0; k < 2; k++)" in result
+
+    def test_nested_for_loops(self) -> None:
+        """Test nested for loops."""
+        outer = ForLoopBody("genvar", "i", 3)
+        inner = ForLoopBody("genvar", "j", 2)
+        inner += "nested_statement;"
+        outer += inner
+
+        result = str(outer)
+        assert "for (genvar i = 0; i < 3; i++)" in result
+        assert "for (genvar j = 0; j < 2; j++)" in result
+        assert "nested_statement;" in result

tests/body/test_if_body.py

@@ -0,0 +1,85 @@
+from peakrdl_busdecoder.body import IfBody
+class TestIfBody:
+    """Test the IfBody class."""
+
+    def test_simple_if(self):
+        """Test simple if statement."""
+        body = IfBody()
+        with body.cm("condition1") as b:
+            b += "statement1;"
+
+        result = str(body)
+        assert "if (condition1)" in result
+        assert "statement1;" in result
+        assert "end" in result
+
+    def test_if_else(self):
+        """Test if-else statement."""
+        body = IfBody()
+        with body.cm("condition1") as b:
+            b += "if_statement;"
+        with body.cm(None) as b:  # None for else
+            b += "else_statement;"
+
+        result = str(body)
+        assert "if (condition1)" in result
+        assert "if_statement;" in result
+        assert "else" in result
+        assert "else_statement;" in result
+
+    def test_if_elif_else(self):
+        """Test if-elif-else chain."""
+        body = IfBody()
+        with body.cm("condition1") as b:
+            b += "statement1;"
+        with body.cm("condition2") as b:
+            b += "statement2;"
+        with body.cm(None) as b:  # None for else
+            b += "statement3;"
+
+        result = str(body)
+        assert "if (condition1)" in result
+        assert "statement1;" in result
+        assert "else if (condition2)" in result
+        assert "statement2;" in result
+        assert "else" in result
+        assert "statement3;" in result
+
+    def test_multiple_elif(self):
+        """Test multiple elif statements."""
+        body = IfBody()
+        with body.cm("cond1") as b:
+            b += "stmt1;"
+        with body.cm("cond2") as b:
+            b += "stmt2;"
+        with body.cm("cond3") as b:
+            b += "stmt3;"
+
+        result = str(body)
+        assert "if (cond1)" in result
+        assert "else if (cond2)" in result
+        assert "else if (cond3)" in result
+
+    def test_empty_if_branches(self):
+        """Test if statement with empty branches."""
+        body = IfBody()
+        with body.cm("condition"):
+            pass
+
+        result = str(body)
+        assert "if (condition)" in result
+
+    def test_nested_if(self):
+        """Test nested if statements."""
+        outer = IfBody()
+        with outer.cm("outer_cond") as outer_body:
+            inner = IfBody()
+            with inner.cm("inner_cond") as inner_body:
+                inner_body += "nested_statement;"
+            outer_body += inner
+
+        result = str(outer)
+        assert "if (outer_cond)" in result
+        assert "if (inner_cond)" in result
+        assert "nested_statement;" in result
+

tests/body/test_struct_body.py

@@ -0,0 +1,59 @@
+from peakrdl_busdecoder.body import StructBody
+
+
+class TestStructBody:
+    """Test the StructBody class."""
+
+    def test_simple_struct(self) -> None:
+        """Test simple struct definition."""
+        body = StructBody("my_struct_t", packed=True, typedef=True)
+        body += "logic [7:0] field1;"
+        body += "logic field2;"
+
+        result = str(body)
+        assert "typedef struct packed" in result
+        assert "my_struct_t" in result
+        assert "logic [7:0] field1;" in result
+        assert "logic field2;" in result
+
+    def test_unpacked_struct(self) -> None:
+        """Test unpacked struct definition."""
+        body = StructBody("unpacked_t", packed=False, typedef=True)
+        body += "int field1;"
+
+        result = str(body)
+        assert "typedef struct" in result
+        assert "packed" not in result or "typedef struct {" in result
+        assert "unpacked_t" in result
+
+    def test_struct_without_typedef(self) -> None:
+        """Test struct without typedef."""
+        body = StructBody("my_struct", packed=True, typedef=False)
+        body += "logic field;"
+
+        result = str(body)
+        # When typedef=False, packed is not used
+        assert "struct {" in result
+        assert "typedef" not in result
+        assert "my_struct" in result
+
+    def test_empty_struct(self) -> None:
+        """Test empty struct."""
+        body = StructBody("empty_t", packed=True, typedef=True)
+        result = str(body)
+        assert "typedef struct packed" in result
+        assert "empty_t" in result
+
+    def test_nested_struct(self) -> None:
+        """Test struct with nested struct."""
+        outer = StructBody("outer_t", packed=True, typedef=True)
+        inner = StructBody("inner_t", packed=True, typedef=True)
+        inner += "logic field1;"
+        outer += "logic field2;"
+        outer += str(inner)  # Include inner struct as a string
+
+        result = str(outer)
+        assert "outer_t" in result
+        assert "field2;" in result
+        # Inner struct should appear in the string
+        assert "inner_t" in result

tests/cocotb/apb3/smoke/test_register_access.py

@@ -0,0 +1,186 @@
+"""APB3 smoke tests generated from SystemRDL sources."""
+
+from __future__ import annotations
+
+import json
+import os
+from typing import Any, Iterable
+
+import cocotb
+from cocotb.triggers import Timer
+
+from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
+
+class _Apb3SlaveShim:
+    """Accessor for the APB3 slave signals on the DUT."""
+
+    def __init__(self, dut):
+        prefix = "s_apb"
+        self.PSEL = getattr(dut, f"{prefix}_PSEL")
+        self.PENABLE = getattr(dut, f"{prefix}_PENABLE")
+        self.PWRITE = getattr(dut, f"{prefix}_PWRITE")
+        self.PADDR = getattr(dut, f"{prefix}_PADDR")
+        self.PWDATA = getattr(dut, f"{prefix}_PWDATA")
+        self.PRDATA = getattr(dut, f"{prefix}_PRDATA")
+        self.PREADY = getattr(dut, f"{prefix}_PREADY")
+        self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
+
+
+def _load_config() -> dict[str, Any]:
+    payload = os.environ.get("RDL_TEST_CONFIG")
+    if payload is None:
+        raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
+    return json.loads(payload)
+
+
+def _resolve(handle, indices: Iterable[int]):
+    return resolve_handle(handle, indices)
+
+
+def _set_value(handle, indices: Iterable[int], value: int) -> None:
+    _resolve(handle, indices).value = value
+
+
+def _get_int(handle, indices: Iterable[int]) -> int:
+    return int(_resolve(handle, indices).value)
+
+
+def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
+    table: dict[str, dict[str, Any]] = {}
+    for master in masters_cfg:
+        prefix = master["port_prefix"]
+        entry = {
+            "indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
+            "outputs": {
+                "PSEL": SignalHandle(dut, f"{prefix}_PSEL"),
+                "PENABLE": SignalHandle(dut, f"{prefix}_PENABLE"),
+                "PWRITE": SignalHandle(dut, f"{prefix}_PWRITE"),
+                "PADDR": SignalHandle(dut, f"{prefix}_PADDR"),
+                "PWDATA": SignalHandle(dut, f"{prefix}_PWDATA"),
+            },
+            "inputs": {
+                "PRDATA": SignalHandle(dut, f"{prefix}_PRDATA"),
+                "PREADY": SignalHandle(dut, f"{prefix}_PREADY"),
+                "PSLVERR": SignalHandle(dut, f"{prefix}_PSLVERR"),
+            },
+        }
+        table[master["inst_name"]] = entry
+    return table
+
+
+def _all_index_pairs(table: dict[str, dict[str, Any]]):
+    for name, entry in table.items():
+        for idx in entry["indices"]:
+            yield name, idx
+
+
+def _write_pattern(address: int, width: int) -> int:
+    mask = (1 << width) - 1
+    return ((address * 0x2041) ^ 0xCAFEBABE) & mask
+
+
+def _read_pattern(address: int, width: int) -> int:
+    mask = (1 << width) - 1
+    return ((address ^ 0x0BAD_F00D) + width) & mask
+
+
+@cocotb.test()
+async def test_apb3_address_decoding(dut) -> None:
+    """Exercise the APB3 slave interface against sampled register addresses."""
+    config = _load_config()
+    slave = _Apb3SlaveShim(dut)
+    masters = _build_master_table(dut, config["masters"])
+
+    slave.PSEL.value = 0
+    slave.PENABLE.value = 0
+    slave.PWRITE.value = 0
+    slave.PADDR.value = 0
+    slave.PWDATA.value = 0
+
+    for master_name, idx in _all_index_pairs(masters):
+        entry = masters[master_name]
+        _set_value(entry["inputs"]["PRDATA"], idx, 0)
+        _set_value(entry["inputs"]["PREADY"], idx, 0)
+        _set_value(entry["inputs"]["PSLVERR"], idx, 0)
+
+    await Timer(1, units="ns")
+
+    addr_mask = (1 << config["address_width"]) - 1
+
+    for txn in config["transactions"]:
+        master_name = txn["master"]
+        index = tuple(txn["index"])
+        entry = masters[master_name]
+
+        address = txn["address"] & addr_mask
+        write_data = _write_pattern(address, config["data_width"])
+
+        _set_value(entry["inputs"]["PREADY"], index, 1)
+        _set_value(entry["inputs"]["PSLVERR"], index, 0)
+
+        slave.PADDR.value = address
+        slave.PWDATA.value = write_data
+        slave.PWRITE.value = 1
+        slave.PSEL.value = 1
+        slave.PENABLE.value = 1
+
+        await Timer(1, units="ns")
+
+        assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
+        assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write direction"
+        assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive write address"
+        assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, f"{master_name} must receive write data"
+
+        for other_name, other_idx in _all_index_pairs(masters):
+            if other_name == master_name and other_idx == index:
+                continue
+            other_entry = masters[other_name]
+            assert (
+                _get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
+            ), f"{other_name}{other_idx} should remain idle during {txn['label']}"
+
+        assert int(slave.PREADY.value) == 1, "Slave ready should mirror selected master"
+        assert int(slave.PSLVERR.value) == 0, "Write should complete without error"
+
+        slave.PSEL.value = 0
+        slave.PENABLE.value = 0
+        slave.PWRITE.value = 0
+        _set_value(entry["inputs"]["PREADY"], index, 0)
+        await Timer(1, units="ns")
+
+        # ------------------------------------------------------------------
+        # Read phase
+        # ------------------------------------------------------------------
+        read_data = _read_pattern(address, config["data_width"])
+        _set_value(entry["inputs"]["PRDATA"], index, read_data)
+        _set_value(entry["inputs"]["PREADY"], index, 1)
+        _set_value(entry["inputs"]["PSLVERR"], index, 0)
+
+        slave.PADDR.value = address
+        slave.PWRITE.value = 0
+        slave.PSEL.value = 1
+        slave.PENABLE.value = 1
+
+        await Timer(1, units="ns")
+
+        assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
+        assert _get_int(entry["outputs"]["PWRITE"], index) == 0, f"{master_name} should clear write during read"
+        assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive read address"
+
+        for other_name, other_idx in _all_index_pairs(masters):
+            if other_name == master_name and other_idx == index:
+                continue
+            other_entry = masters[other_name]
+            assert (
+                _get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
+            ), f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
+
+        assert int(slave.PRDATA.value) == read_data, "Read data should propagate back to the slave"
+        assert int(slave.PREADY.value) == 1, "Slave ready should acknowledge the read"
+        assert int(slave.PSLVERR.value) == 0, "Read should not signal an error"
+
+        slave.PSEL.value = 0
+        slave.PENABLE.value = 0
+        _set_value(entry["inputs"]["PREADY"], index, 0)
+        _set_value(entry["inputs"]["PRDATA"], index, 0)
+        await Timer(1, units="ns")

tests/cocotb/apb3/smoke/test_runner.py

@@ -0,0 +1,59 @@
+"""Pytest wrapper launching the APB3 cocotb smoke tests."""
+
+from __future__ import annotations
+
+import json
+from pathlib import Path
+
+import pytest
+
+from peakrdl_busdecoder.cpuif.apb3.apb3_cpuif_flat import APB3CpuifFlat
+
+try:  # pragma: no cover - optional dependency shim
+    from cocotb.runner import get_runner
+except ImportError:  # pragma: no cover
+    from cocotb_tools.runner import get_runner
+
+from tests.cocotb_lib import RDL_CASES
+from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
+def test_apb3_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
+    """Compile each APB3 design variant and execute the cocotb smoke test."""
+    repo_root = Path(__file__).resolve().parents[4]
+    rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
+    build_root = tmp_path / top_name
+
+    module_path, package_path, config = prepare_cpuif_case(
+        str(rdl_path),
+        top_name,
+        build_root,
+        cpuif_cls=APB3CpuifFlat,
+        control_signal="PSEL",
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb3_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    sim_build = build_root / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=sim_build,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb3.smoke.test_register_access",
+        build_dir=sim_build,
+        log_file=str(build_root / "simulation.log"),
+        extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
+    )

tests/cocotb/apb3/smoke/test_variable_depth.py

@@ -0,0 +1,211 @@
+"""APB3 smoke tests for variable depth design testing max_decode_depth parameter."""
+
+import cocotb
+from cocotb.triggers import Timer
+
+
+class _Apb3SlaveShim:
+    def __init__(self, dut):
+        prefix = "s_apb"
+        self.PSEL = getattr(dut, f"{prefix}_PSEL")
+        self.PENABLE = getattr(dut, f"{prefix}_PENABLE")
+        self.PWRITE = getattr(dut, f"{prefix}_PWRITE")
+        self.PADDR = getattr(dut, f"{prefix}_PADDR")
+        self.PWDATA = getattr(dut, f"{prefix}_PWDATA")
+        self.PRDATA = getattr(dut, f"{prefix}_PRDATA")
+        self.PREADY = getattr(dut, f"{prefix}_PREADY")
+        self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
+
+
+class _Apb3MasterShim:
+    def __init__(self, dut, base: str):
+        self.PSEL = getattr(dut, f"{base}_PSEL")
+        self.PENABLE = getattr(dut, f"{base}_PENABLE")
+        self.PWRITE = getattr(dut, f"{base}_PWRITE")
+        self.PADDR = getattr(dut, f"{base}_PADDR")
+        self.PWDATA = getattr(dut, f"{base}_PWDATA")
+        self.PRDATA = getattr(dut, f"{base}_PRDATA")
+        self.PREADY = getattr(dut, f"{base}_PREADY")
+        self.PSLVERR = getattr(dut, f"{base}_PSLVERR")
+
+
+def _apb3_slave(dut):
+    return getattr(dut, "s_apb", None) or _Apb3SlaveShim(dut)
+
+
+def _apb3_master(dut, base: str):
+    return getattr(dut, base, None) or _Apb3MasterShim(dut, base)
+
+
+@cocotb.test()
+async def test_depth_1(dut):
+    """Test max_decode_depth=1 - should have interface for inner1 only."""
+    s_apb = _apb3_slave(dut)
+    
+    # At depth 1, we should have m_apb_inner1 but not deeper interfaces
+    inner1 = _apb3_master(dut, "m_apb_inner1")
+    
+    # Default slave side inputs
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    s_apb.PADDR.value = 0
+    s_apb.PWDATA.value = 0
+    
+    inner1.PRDATA.value = 0
+    inner1.PREADY.value = 0
+    inner1.PSLVERR.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select inner1)
+    inner1.PREADY.value = 1
+    s_apb.PADDR.value = 0x0
+    s_apb.PWDATA.value = 0x12345678
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(inner1.PSEL.value) == 1, "inner1 must be selected"
+    assert int(inner1.PWRITE.value) == 1, "Write should propagate"
+    assert int(s_apb.PREADY.value) == 1, "Ready should mirror master"
+
+
+@cocotb.test()
+async def test_depth_2(dut):
+    """Test max_decode_depth=2 - should have interfaces for reg1 and inner2."""
+    s_apb = _apb3_slave(dut)
+    
+    # At depth 2, we should have m_apb_reg1 and m_apb_inner2
+    reg1 = _apb3_master(dut, "m_apb_reg1")
+    inner2 = _apb3_master(dut, "m_apb_inner2")
+    
+    # Default slave side inputs
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    s_apb.PADDR.value = 0
+    s_apb.PWDATA.value = 0
+    
+    reg1.PRDATA.value = 0
+    reg1.PREADY.value = 0
+    reg1.PSLVERR.value = 0
+    
+    inner2.PRDATA.value = 0
+    inner2.PREADY.value = 0
+    inner2.PSLVERR.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select reg1)
+    reg1.PREADY.value = 1
+    s_apb.PADDR.value = 0x0
+    s_apb.PWDATA.value = 0xABCDEF01
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
+    assert int(inner2.PSEL.value) == 0, "inner2 should not be selected"
+    
+    # Reset
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    reg1.PREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x10 (should select inner2)
+    inner2.PREADY.value = 1
+    s_apb.PADDR.value = 0x10
+    s_apb.PWDATA.value = 0x23456789
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(inner2.PSEL.value) == 1, "inner2 must be selected for address 0x10"
+    assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
+
+
+@cocotb.test()
+async def test_depth_0(dut):
+    """Test max_decode_depth=0 - should have interfaces for all leaf registers."""
+    s_apb = _apb3_slave(dut)
+    
+    # At depth 0, we should have all leaf registers: reg1, reg2, reg2b
+    reg1 = _apb3_master(dut, "m_apb_reg1")
+    reg2 = _apb3_master(dut, "m_apb_reg2")
+    reg2b = _apb3_master(dut, "m_apb_reg2b")
+    
+    # Default slave side inputs
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    s_apb.PADDR.value = 0
+    s_apb.PWDATA.value = 0
+    
+    for master in [reg1, reg2, reg2b]:
+        master.PRDATA.value = 0
+        master.PREADY.value = 0
+        master.PSLVERR.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select reg1)
+    reg1.PREADY.value = 1
+    s_apb.PADDR.value = 0x0
+    s_apb.PWDATA.value = 0x11111111
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
+    assert int(reg2.PSEL.value) == 0, "reg2 should not be selected"
+    assert int(reg2b.PSEL.value) == 0, "reg2b should not be selected"
+    
+    # Reset
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    reg1.PREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x10 (should select reg2)
+    reg2.PREADY.value = 1
+    s_apb.PADDR.value = 0x10
+    s_apb.PWDATA.value = 0x22222222
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg2.PSEL.value) == 1, "reg2 must be selected for address 0x10"
+    assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
+    assert int(reg2b.PSEL.value) == 0, "reg2b should not be selected"
+    
+    # Reset
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    reg2.PREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x14 (should select reg2b)
+    reg2b.PREADY.value = 1
+    s_apb.PADDR.value = 0x14
+    s_apb.PWDATA.value = 0x33333333
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg2b.PSEL.value) == 1, "reg2b must be selected for address 0x14"
+    assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
+    assert int(reg2.PSEL.value) == 0, "reg2 should not be selected"

tests/cocotb/apb3/smoke/test_variable_depth_runner.py

@@ -0,0 +1,128 @@
+"""Pytest wrapper launching the APB3 cocotb smoke test for variable depth."""
+
+from pathlib import Path
+
+import pytest
+
+from peakrdl_busdecoder.cpuif.apb3.apb3_cpuif_flat import APB3CpuifFlat
+
+try:  # pragma: no cover - optional dependency shim
+    from cocotb.runner import get_runner
+except ImportError:  # pragma: no cover
+    from cocotb_tools.runner import get_runner
+
+from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_apb3_variable_depth_1(tmp_path: Path) -> None:
+    """Test APB3 design with max_decode_depth=1."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=APB3CpuifFlat,
+        max_decode_depth=1,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb3_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb3.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth1.log"),
+        testcase="test_depth_1",
+    )
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_apb3_variable_depth_2(tmp_path: Path) -> None:
+    """Test APB3 design with max_decode_depth=2."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=APB3CpuifFlat,
+        max_decode_depth=2,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb3_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb3.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth2.log"),
+        testcase="test_depth_2",
+    )
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_apb3_variable_depth_0(tmp_path: Path) -> None:
+    """Test APB3 design with max_decode_depth=0 (all levels)."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=APB3CpuifFlat,
+        max_decode_depth=0,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb3_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb3.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth0.log"),
+        testcase="test_depth_0",
+    )

tests/cocotb/apb4/smoke/test_register_access.py

@@ -0,0 +1,202 @@
+"""APB4 smoke tests generated from SystemRDL sources."""
+
+from __future__ import annotations
+
+import json
+import os
+from typing import Any, Iterable
+
+import cocotb
+from cocotb.triggers import Timer
+
+from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
+
+class _Apb4SlaveShim:
+    """Lightweight accessor for the APB4 slave side of the DUT."""
+
+    def __init__(self, dut):
+        prefix = "s_apb"
+        self.PSEL = getattr(dut, f"{prefix}_PSEL")
+        self.PENABLE = getattr(dut, f"{prefix}_PENABLE")
+        self.PWRITE = getattr(dut, f"{prefix}_PWRITE")
+        self.PADDR = getattr(dut, f"{prefix}_PADDR")
+        self.PPROT = getattr(dut, f"{prefix}_PPROT")
+        self.PWDATA = getattr(dut, f"{prefix}_PWDATA")
+        self.PSTRB = getattr(dut, f"{prefix}_PSTRB")
+        self.PRDATA = getattr(dut, f"{prefix}_PRDATA")
+        self.PREADY = getattr(dut, f"{prefix}_PREADY")
+        self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
+
+
+def _load_config() -> dict[str, Any]:
+    """Read the JSON payload describing the generated register topology."""
+    payload = os.environ.get("RDL_TEST_CONFIG")
+    if payload is None:
+        raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
+    return json.loads(payload)
+
+
+def _resolve(handle, indices: Iterable[int]):
+    """Index into hierarchical cocotb handles."""
+    return resolve_handle(handle, indices)
+
+
+def _set_value(handle, indices: Iterable[int], value: int) -> None:
+    _resolve(handle, indices).value = value
+
+
+def _get_int(handle, indices: Iterable[int]) -> int:
+    return int(_resolve(handle, indices).value)
+
+
+def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
+    table: dict[str, dict[str, Any]] = {}
+    for master in masters_cfg:
+        port_prefix = master["port_prefix"]
+        entry = {
+            "port_prefix": port_prefix,
+            "indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
+            "outputs": {
+                "PSEL": SignalHandle(dut, f"{port_prefix}_PSEL"),
+                "PENABLE": SignalHandle(dut, f"{port_prefix}_PENABLE"),
+                "PWRITE": SignalHandle(dut, f"{port_prefix}_PWRITE"),
+                "PADDR": SignalHandle(dut, f"{port_prefix}_PADDR"),
+                "PPROT": SignalHandle(dut, f"{port_prefix}_PPROT"),
+                "PWDATA": SignalHandle(dut, f"{port_prefix}_PWDATA"),
+                "PSTRB": SignalHandle(dut, f"{port_prefix}_PSTRB"),
+            },
+            "inputs": {
+                "PRDATA": SignalHandle(dut, f"{port_prefix}_PRDATA"),
+                "PREADY": SignalHandle(dut, f"{port_prefix}_PREADY"),
+                "PSLVERR": SignalHandle(dut, f"{port_prefix}_PSLVERR"),
+            },
+        }
+        table[master["inst_name"]] = entry
+    return table
+
+
+def _all_index_pairs(table: dict[str, dict[str, Any]]):
+    for name, entry in table.items():
+        for idx in entry["indices"]:
+            yield name, idx
+
+
+def _write_pattern(address: int, width: int) -> int:
+    mask = (1 << width) - 1
+    return ((address * 0x1021) ^ 0x1357_9BDF) & mask
+
+
+def _read_pattern(address: int, width: int) -> int:
+    mask = (1 << width) - 1
+    return ((address ^ 0xDEAD_BEE5) + width) & mask
+
+
+@cocotb.test()
+async def test_apb4_address_decoding(dut) -> None:
+    """Drive the APB4 slave interface and verify master fanout across all sampled registers."""
+    config = _load_config()
+    slave = _Apb4SlaveShim(dut)
+    masters = _build_master_table(dut, config["masters"])
+
+    slave.PSEL.value = 0
+    slave.PENABLE.value = 0
+    slave.PWRITE.value = 0
+    slave.PADDR.value = 0
+    slave.PPROT.value = 0
+    slave.PWDATA.value = 0
+    slave.PSTRB.value = 0
+
+    for master_name, idx in _all_index_pairs(masters):
+        entry = masters[master_name]
+        _set_value(entry["inputs"]["PRDATA"], idx, 0)
+        _set_value(entry["inputs"]["PREADY"], idx, 0)
+        _set_value(entry["inputs"]["PSLVERR"], idx, 0)
+
+    await Timer(1, units="ns")
+
+    addr_mask = (1 << config["address_width"]) - 1
+    strobe_mask = (1 << config["byte_width"]) - 1
+
+    for txn in config["transactions"]:
+        master_name = txn["master"]
+        index = tuple(txn["index"])
+        entry = masters[master_name]
+
+        address = txn["address"] & addr_mask
+        write_data = _write_pattern(address, config["data_width"])
+
+        # Prime master-side inputs for the write phase
+        _set_value(entry["inputs"]["PREADY"], index, 1)
+        _set_value(entry["inputs"]["PSLVERR"], index, 0)
+
+        slave.PADDR.value = address
+        slave.PWDATA.value = write_data
+        slave.PSTRB.value = strobe_mask
+        slave.PPROT.value = 0
+        slave.PWRITE.value = 1
+        slave.PSEL.value = 1
+        slave.PENABLE.value = 1
+
+        await Timer(1, units="ns")
+
+        assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} should assert PSEL for write"
+        assert _get_int(entry["outputs"]["PWRITE"], index) == 1, f"{master_name} should see write intent"
+        assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive write address"
+        assert _get_int(entry["outputs"]["PWDATA"], index) == write_data, f"{master_name} must receive write data"
+        assert _get_int(entry["outputs"]["PSTRB"], index) == strobe_mask, f"{master_name} must receive full strobes"
+
+        for other_name, other_idx in _all_index_pairs(masters):
+            if other_name == master_name and other_idx == index:
+                continue
+            other_entry = masters[other_name]
+            assert (
+                _get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
+            ), f"{other_name}{other_idx} should remain idle during {txn['label']}"
+
+        assert int(slave.PREADY.value) == 1, "Slave ready should reflect selected master"
+        assert int(slave.PSLVERR.value) == 0, "No error expected during write"
+
+        # Return to idle for next transaction
+        slave.PSEL.value = 0
+        slave.PENABLE.value = 0
+        slave.PWRITE.value = 0
+        _set_value(entry["inputs"]["PREADY"], index, 0)
+        await Timer(1, units="ns")
+
+        # ------------------------------------------------------------------
+        # Read phase
+        # ------------------------------------------------------------------
+        read_data = _read_pattern(address, config["data_width"])
+        _set_value(entry["inputs"]["PRDATA"], index, read_data)
+        _set_value(entry["inputs"]["PREADY"], index, 1)
+        _set_value(entry["inputs"]["PSLVERR"], index, 0)
+
+        slave.PADDR.value = address
+        slave.PWRITE.value = 0
+        slave.PSEL.value = 1
+        slave.PENABLE.value = 1
+
+        await Timer(1, units="ns")
+
+        assert _get_int(entry["outputs"]["PSEL"], index) == 1, f"{master_name} must assert PSEL for read"
+        assert _get_int(entry["outputs"]["PWRITE"], index) == 0, f"{master_name} should deassert write for reads"
+        assert _get_int(entry["outputs"]["PADDR"], index) == address, f"{master_name} must receive read address"
+
+        for other_name, other_idx in _all_index_pairs(masters):
+            if other_name == master_name and other_idx == index:
+                continue
+            other_entry = masters[other_name]
+            assert (
+                _get_int(other_entry["outputs"]["PSEL"], other_idx) == 0
+            ), f"{other_name}{other_idx} must stay idle during read of {txn['label']}"
+
+        assert int(slave.PRDATA.value) == read_data, "Slave should observe readback data from master"
+        assert int(slave.PREADY.value) == 1, "Slave ready should follow responding master"
+        assert int(slave.PSLVERR.value) == 0, "Read should complete without error"
+
+        # Reset to idle before progressing
+        slave.PSEL.value = 0
+        slave.PENABLE.value = 0
+        _set_value(entry["inputs"]["PREADY"], index, 0)
+        _set_value(entry["inputs"]["PRDATA"], index, 0)
+        await Timer(1, units="ns")

tests/cocotb/apb4/smoke/test_runner.py

@@ -0,0 +1,80 @@
+"""Pytest wrapper launching the APB4 cocotb smoke tests."""
+
+from __future__ import annotations
+
+import json
+from pathlib import Path
+import logging
+import pytest
+
+from peakrdl_busdecoder.cpuif.apb4.apb4_cpuif_flat import APB4CpuifFlat
+
+try:  # pragma: no cover - optional dependency shim
+    from cocotb.runner import get_runner
+except ImportError:  # pragma: no cover
+    from cocotb_tools.runner import get_runner
+
+from tests.cocotb_lib import RDL_CASES
+from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
+def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
+    """Compile each APB4 design variant and execute the cocotb smoke test."""
+    repo_root = Path(__file__).resolve().parents[4]
+    rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
+    build_root = tmp_path / top_name
+
+    module_path, package_path, config = prepare_cpuif_case(
+        str(rdl_path),
+        top_name,
+        build_root,
+        cpuif_cls=APB4CpuifFlat,
+        control_signal="PSEL",
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb4_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    sim_build = build_root / "sim_build"
+    
+    try:
+        runner.build(
+            sources=sources,
+            hdl_toplevel=module_path.stem,
+            build_dir=sim_build,
+            log_file=str(build_root / "build.log"),
+        )
+    except SystemExit as e:
+        # Print build log on failure for easier debugging
+        log_path = build_root / "build.log"
+        if log_path.exists():
+            logging.error("\n\n=== Build Log ===\n")
+            logging.error(log_path.read_text())
+            logging.error("\n=== End Build Log ===\n")
+        if e.code != 0:
+            raise
+
+    try:
+        runner.test(
+            hdl_toplevel=module_path.stem,
+            test_module="tests.cocotb.apb4.smoke.test_register_access",
+            build_dir=sim_build,
+            log_file=str(build_root / "simulation.log"),
+            extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
+        )
+    except SystemExit as e:
+        # Print simulation log on failure for easier debugging
+        log_path = build_root / "simulation.log"
+        if log_path.exists():
+            logging.error("\n\n=== Simulation Log ===\n")
+            logging.error(log_path.read_text())
+            logging.error("\n=== End Simulation Log ===\n")
+        if e.code != 0:
+            raise

tests/cocotb/apb4/smoke/test_variable_depth.py

@@ -0,0 +1,227 @@
+"""APB4 smoke tests for variable depth design testing max_decode_depth parameter."""
+
+import cocotb
+from cocotb.triggers import Timer
+
+
+class _Apb4SlaveShim:
+    def __init__(self, dut):
+        prefix = "s_apb"
+        self.PSEL = getattr(dut, f"{prefix}_PSEL")
+        self.PENABLE = getattr(dut, f"{prefix}_PENABLE")
+        self.PWRITE = getattr(dut, f"{prefix}_PWRITE")
+        self.PADDR = getattr(dut, f"{prefix}_PADDR")
+        self.PPROT = getattr(dut, f"{prefix}_PPROT")
+        self.PWDATA = getattr(dut, f"{prefix}_PWDATA")
+        self.PSTRB = getattr(dut, f"{prefix}_PSTRB")
+        self.PRDATA = getattr(dut, f"{prefix}_PRDATA")
+        self.PREADY = getattr(dut, f"{prefix}_PREADY")
+        self.PSLVERR = getattr(dut, f"{prefix}_PSLVERR")
+
+
+class _Apb4MasterShim:
+    def __init__(self, dut, base: str):
+        self.PSEL = getattr(dut, f"{base}_PSEL")
+        self.PENABLE = getattr(dut, f"{base}_PENABLE")
+        self.PWRITE = getattr(dut, f"{base}_PWRITE")
+        self.PADDR = getattr(dut, f"{base}_PADDR")
+        self.PPROT = getattr(dut, f"{base}_PPROT")
+        self.PWDATA = getattr(dut, f"{base}_PWDATA")
+        self.PSTRB = getattr(dut, f"{base}_PSTRB")
+        self.PRDATA = getattr(dut, f"{base}_PRDATA")
+        self.PREADY = getattr(dut, f"{base}_PREADY")
+        self.PSLVERR = getattr(dut, f"{base}_PSLVERR")
+
+
+def _apb4_slave(dut):
+    return getattr(dut, "s_apb", None) or _Apb4SlaveShim(dut)
+
+
+def _apb4_master(dut, base: str):
+    return getattr(dut, base, None) or _Apb4MasterShim(dut, base)
+
+
+@cocotb.test()
+async def test_depth_1(dut):
+    """Test max_decode_depth=1 - should have interface for inner1 only."""
+    s_apb = _apb4_slave(dut)
+    
+    # At depth 1, we should have m_apb_inner1 but not deeper interfaces
+    inner1 = _apb4_master(dut, "m_apb_inner1")
+    
+    # Default slave side inputs
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    s_apb.PADDR.value = 0
+    s_apb.PWDATA.value = 0
+    s_apb.PPROT.value = 0
+    s_apb.PSTRB.value = 0
+    
+    inner1.PRDATA.value = 0
+    inner1.PREADY.value = 0
+    inner1.PSLVERR.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select inner1)
+    inner1.PREADY.value = 1
+    s_apb.PADDR.value = 0x0
+    s_apb.PWDATA.value = 0x12345678
+    s_apb.PSTRB.value = 0xF
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(inner1.PSEL.value) == 1, "inner1 must be selected"
+    assert int(inner1.PWRITE.value) == 1, "Write should propagate"
+    assert int(s_apb.PREADY.value) == 1, "Ready should mirror master"
+
+
+@cocotb.test()
+async def test_depth_2(dut):
+    """Test max_decode_depth=2 - should have interfaces for reg1 and inner2."""
+    s_apb = _apb4_slave(dut)
+    
+    # At depth 2, we should have m_apb_reg1 and m_apb_inner2
+    reg1 = _apb4_master(dut, "m_apb_reg1")
+    inner2 = _apb4_master(dut, "m_apb_inner2")
+    
+    # Default slave side inputs
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    s_apb.PADDR.value = 0
+    s_apb.PWDATA.value = 0
+    s_apb.PPROT.value = 0
+    s_apb.PSTRB.value = 0
+    
+    reg1.PRDATA.value = 0
+    reg1.PREADY.value = 0
+    reg1.PSLVERR.value = 0
+    
+    inner2.PRDATA.value = 0
+    inner2.PREADY.value = 0
+    inner2.PSLVERR.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select reg1)
+    reg1.PREADY.value = 1
+    s_apb.PADDR.value = 0x0
+    s_apb.PWDATA.value = 0xABCDEF01
+    s_apb.PSTRB.value = 0xF
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
+    assert int(inner2.PSEL.value) == 0, "inner2 should not be selected"
+    
+    # Reset
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    reg1.PREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x10 (should select inner2)
+    inner2.PREADY.value = 1
+    s_apb.PADDR.value = 0x10
+    s_apb.PWDATA.value = 0x23456789
+    s_apb.PSTRB.value = 0xF
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(inner2.PSEL.value) == 1, "inner2 must be selected for address 0x10"
+    assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
+
+
+@cocotb.test()
+async def test_depth_0(dut):
+    """Test max_decode_depth=0 - should have interfaces for all leaf registers."""
+    s_apb = _apb4_slave(dut)
+    
+    # At depth 0, we should have all leaf registers: reg1, reg2, reg2b
+    reg1 = _apb4_master(dut, "m_apb_reg1")
+    reg2 = _apb4_master(dut, "m_apb_reg2")
+    reg2b = _apb4_master(dut, "m_apb_reg2b")
+    
+    # Default slave side inputs
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    s_apb.PWRITE.value = 0
+    s_apb.PADDR.value = 0
+    s_apb.PWDATA.value = 0
+    s_apb.PPROT.value = 0
+    s_apb.PSTRB.value = 0
+    
+    for master in [reg1, reg2, reg2b]:
+        master.PRDATA.value = 0
+        master.PREADY.value = 0
+        master.PSLVERR.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select reg1)
+    reg1.PREADY.value = 1
+    s_apb.PADDR.value = 0x0
+    s_apb.PWDATA.value = 0x11111111
+    s_apb.PSTRB.value = 0xF
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg1.PSEL.value) == 1, "reg1 must be selected for address 0x0"
+    assert int(reg2.PSEL.value) == 0, "reg2 should not be selected"
+    assert int(reg2b.PSEL.value) == 0, "reg2b should not be selected"
+    
+    # Reset
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    reg1.PREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x10 (should select reg2)
+    reg2.PREADY.value = 1
+    s_apb.PADDR.value = 0x10
+    s_apb.PWDATA.value = 0x22222222
+    s_apb.PSTRB.value = 0xF
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg2.PSEL.value) == 1, "reg2 must be selected for address 0x10"
+    assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
+    assert int(reg2b.PSEL.value) == 0, "reg2b should not be selected"
+    
+    # Reset
+    s_apb.PSEL.value = 0
+    s_apb.PENABLE.value = 0
+    reg2.PREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x14 (should select reg2b)
+    reg2b.PREADY.value = 1
+    s_apb.PADDR.value = 0x14
+    s_apb.PWDATA.value = 0x33333333
+    s_apb.PSTRB.value = 0xF
+    s_apb.PWRITE.value = 1
+    s_apb.PSEL.value = 1
+    s_apb.PENABLE.value = 1
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg2b.PSEL.value) == 1, "reg2b must be selected for address 0x14"
+    assert int(reg1.PSEL.value) == 0, "reg1 should not be selected"
+    assert int(reg2.PSEL.value) == 0, "reg2 should not be selected"

tests/cocotb/apb4/smoke/test_variable_depth_runner.py

@@ -0,0 +1,131 @@
+"""Pytest wrapper launching the APB4 cocotb smoke test for variable depth."""
+
+from pathlib import Path
+
+import pytest
+
+from peakrdl_busdecoder.cpuif.apb4.apb4_cpuif_flat import APB4CpuifFlat
+
+try:  # pragma: no cover - optional dependency shim
+    from cocotb.runner import get_runner
+except ImportError:  # pragma: no cover
+    from cocotb_tools.runner import get_runner
+
+from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_apb4_variable_depth_1(tmp_path: Path) -> None:
+    """Test APB4 design with max_decode_depth=1."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=APB4CpuifFlat,
+        max_decode_depth=1,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb4_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+        log_file=str(tmp_path / "build_depth_1.log"),
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb4.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth1.log"),
+        testcase="test_depth_1",
+    )
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_apb4_variable_depth_2(tmp_path: Path) -> None:
+    """Test APB4 design with max_decode_depth=2."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=APB4CpuifFlat,
+        max_decode_depth=2,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb4_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+        log_file=str(tmp_path / "build_depth_2.log"),
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb4.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth_2.log"),
+        testcase="test_depth_2",
+    )
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_apb4_variable_depth_0(tmp_path: Path) -> None:
+    """Test APB4 design with max_decode_depth=0 (all levels)."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=APB4CpuifFlat,
+        max_decode_depth=0,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "apb4_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+        log_file=str(tmp_path / "build_depth_0.log"),
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.apb4.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth_0.log"),
+        testcase="test_depth_0",
+    )

tests/cocotb/axi4lite/smoke/test_register_access.py

@@ -0,0 +1,213 @@
+"""AXI4-Lite smoke test driven from SystemRDL-generated register maps."""
+
+from __future__ import annotations
+
+import json
+import os
+from typing import Any, Iterable
+
+import cocotb
+from cocotb.triggers import Timer
+
+from tests.cocotb_lib.handle_utils import SignalHandle, resolve_handle
+
+class _AxilSlaveShim:
+    """Accessor for AXI4-Lite slave ports on the DUT."""
+
+    def __init__(self, dut):
+        prefix = "s_axil"
+        self.AWREADY = getattr(dut, f"{prefix}_AWREADY")
+        self.AWVALID = getattr(dut, f"{prefix}_AWVALID")
+        self.AWADDR = getattr(dut, f"{prefix}_AWADDR")
+        self.AWPROT = getattr(dut, f"{prefix}_AWPROT")
+        self.WREADY = getattr(dut, f"{prefix}_WREADY")
+        self.WVALID = getattr(dut, f"{prefix}_WVALID")
+        self.WDATA = getattr(dut, f"{prefix}_WDATA")
+        self.WSTRB = getattr(dut, f"{prefix}_WSTRB")
+        self.BREADY = getattr(dut, f"{prefix}_BREADY")
+        self.BVALID = getattr(dut, f"{prefix}_BVALID")
+        self.BRESP = getattr(dut, f"{prefix}_BRESP")
+        self.ARREADY = getattr(dut, f"{prefix}_ARREADY")
+        self.ARVALID = getattr(dut, f"{prefix}_ARVALID")
+        self.ARADDR = getattr(dut, f"{prefix}_ARADDR")
+        self.ARPROT = getattr(dut, f"{prefix}_ARPROT")
+        self.RREADY = getattr(dut, f"{prefix}_RREADY")
+        self.RVALID = getattr(dut, f"{prefix}_RVALID")
+        self.RDATA = getattr(dut, f"{prefix}_RDATA")
+        self.RRESP = getattr(dut, f"{prefix}_RRESP")
+
+
+def _load_config() -> dict[str, Any]:
+    payload = os.environ.get("RDL_TEST_CONFIG")
+    if payload is None:
+        raise RuntimeError("RDL_TEST_CONFIG environment variable was not provided")
+    return json.loads(payload)
+
+
+def _resolve(handle, indices: Iterable[int]):
+    return resolve_handle(handle, indices)
+
+
+def _set_value(handle, indices: Iterable[int], value: int) -> None:
+    _resolve(handle, indices).value = value
+
+
+def _get_int(handle, indices: Iterable[int]) -> int:
+    return int(_resolve(handle, indices).value)
+
+
+def _build_master_table(dut, masters_cfg: list[dict[str, Any]]) -> dict[str, dict[str, Any]]:
+    table: dict[str, dict[str, Any]] = {}
+    for master in masters_cfg:
+        prefix = master["port_prefix"]
+        entry = {
+            "indices": [tuple(idx) for idx in master["indices"]] or [tuple()],
+            "outputs": {
+                "AWVALID": SignalHandle(dut, f"{prefix}_AWVALID"),
+                "AWADDR": SignalHandle(dut, f"{prefix}_AWADDR"),
+                "AWPROT": SignalHandle(dut, f"{prefix}_AWPROT"),
+                "WVALID": SignalHandle(dut, f"{prefix}_WVALID"),
+                "WDATA": SignalHandle(dut, f"{prefix}_WDATA"),
+                "WSTRB": SignalHandle(dut, f"{prefix}_WSTRB"),
+                "ARVALID": SignalHandle(dut, f"{prefix}_ARVALID"),
+                "ARADDR": SignalHandle(dut, f"{prefix}_ARADDR"),
+                "ARPROT": SignalHandle(dut, f"{prefix}_ARPROT"),
+            },
+            "inputs": {
+                "AWREADY": SignalHandle(dut, f"{prefix}_AWREADY"),
+                "WREADY": SignalHandle(dut, f"{prefix}_WREADY"),
+                "BVALID": SignalHandle(dut, f"{prefix}_BVALID"),
+                "BRESP": SignalHandle(dut, f"{prefix}_BRESP"),
+                "ARREADY": SignalHandle(dut, f"{prefix}_ARREADY"),
+                "RVALID": SignalHandle(dut, f"{prefix}_RVALID"),
+                "RDATA": SignalHandle(dut, f"{prefix}_RDATA"),
+                "RRESP": SignalHandle(dut, f"{prefix}_RRESP"),
+            },
+        }
+        table[master["inst_name"]] = entry
+    return table
+
+
+def _all_index_pairs(table: dict[str, dict[str, Any]]):
+    for name, entry in table.items():
+        for idx in entry["indices"]:
+            yield name, idx
+
+
+def _write_pattern(address: int, width: int) -> int:
+    mask = (1 << width) - 1
+    return ((address * 0x3105) ^ 0x1357_9BDF) & mask
+
+
+def _read_pattern(address: int, width: int) -> int:
+    mask = (1 << width) - 1
+    return ((address ^ 0x2468_ACED) + width) & mask
+
+
+@cocotb.test()
+async def test_axi4lite_address_decoding(dut) -> None:
+    """Stimulate AXI4-Lite slave channels and verify master port selection."""
+    config = _load_config()
+    slave = _AxilSlaveShim(dut)
+    masters = _build_master_table(dut, config["masters"])
+
+    slave.AWVALID.value = 0
+    slave.AWADDR.value = 0
+    slave.AWPROT.value = 0
+    slave.WVALID.value = 0
+    slave.WDATA.value = 0
+    slave.WSTRB.value = 0
+    slave.BREADY.value = 0
+    slave.ARVALID.value = 0
+    slave.ARADDR.value = 0
+    slave.ARPROT.value = 0
+    slave.RREADY.value = 0
+
+    for master_name, idx in _all_index_pairs(masters):
+        entry = masters[master_name]
+        _set_value(entry["inputs"]["AWREADY"], idx, 0)
+        _set_value(entry["inputs"]["WREADY"], idx, 0)
+        _set_value(entry["inputs"]["BVALID"], idx, 0)
+        _set_value(entry["inputs"]["BRESP"], idx, 0)
+        _set_value(entry["inputs"]["ARREADY"], idx, 0)
+        _set_value(entry["inputs"]["RVALID"], idx, 0)
+        _set_value(entry["inputs"]["RDATA"], idx, 0)
+        _set_value(entry["inputs"]["RRESP"], idx, 0)
+
+    await Timer(1, units="ns")
+
+    addr_mask = (1 << config["address_width"]) - 1
+    strobe_mask = (1 << config["byte_width"]) - 1
+
+    for txn in config["transactions"]:
+        master_name = txn["master"]
+        index = tuple(txn["index"])
+        entry = masters[master_name]
+
+        address = txn["address"] & addr_mask
+        write_data = _write_pattern(address, config["data_width"])
+
+        slave.AWADDR.value = address
+        slave.AWPROT.value = 0
+        slave.AWVALID.value = 1
+        slave.WDATA.value = write_data
+        slave.WSTRB.value = strobe_mask
+        slave.WVALID.value = 1
+        slave.BREADY.value = 1
+
+        await Timer(1, units="ns")
+
+        assert _get_int(entry["outputs"]["AWVALID"], index) == 1, f"{master_name} should see AWVALID asserted"
+        assert _get_int(entry["outputs"]["AWADDR"], index) == address, f"{master_name} must receive AWADDR"
+        assert _get_int(entry["outputs"]["WVALID"], index) == 1, f"{master_name} should see WVALID asserted"
+        assert _get_int(entry["outputs"]["WDATA"], index) == write_data, f"{master_name} must receive WDATA"
+        assert _get_int(entry["outputs"]["WSTRB"], index) == strobe_mask, f"{master_name} must receive WSTRB"
+
+        for other_name, other_idx in _all_index_pairs(masters):
+            if other_name == master_name and other_idx == index:
+                continue
+            other_entry = masters[other_name]
+            assert (
+                _get_int(other_entry["outputs"]["AWVALID"], other_idx) == 0
+            ), f"{other_name}{other_idx} AWVALID should remain low during {txn['label']}"
+            assert (
+                _get_int(other_entry["outputs"]["WVALID"], other_idx) == 0
+            ), f"{other_name}{other_idx} WVALID should remain low during {txn['label']}"
+
+        slave.AWVALID.value = 0
+        slave.WVALID.value = 0
+        slave.BREADY.value = 0
+        await Timer(1, units="ns")
+
+        read_data = _read_pattern(address, config["data_width"])
+        _set_value(entry["inputs"]["RVALID"], index, 1)
+        _set_value(entry["inputs"]["RDATA"], index, read_data)
+        _set_value(entry["inputs"]["RRESP"], index, 0)
+
+        slave.ARADDR.value = address
+        slave.ARPROT.value = 0
+        slave.ARVALID.value = 1
+        slave.RREADY.value = 1
+
+        await Timer(1, units="ns")
+
+        assert _get_int(entry["outputs"]["ARVALID"], index) == 1, f"{master_name} should assert ARVALID"
+        assert _get_int(entry["outputs"]["ARADDR"], index) == address, f"{master_name} must receive ARADDR"
+
+        for other_name, other_idx in _all_index_pairs(masters):
+            if other_name == master_name and other_idx == index:
+                continue
+            other_entry = masters[other_name]
+            assert (
+                _get_int(other_entry["outputs"]["ARVALID"], other_idx) == 0
+            ), f"{other_name}{other_idx} ARVALID should remain low during read of {txn['label']}"
+
+        assert int(slave.RVALID.value) == 1, "Slave should observe RVALID when master responds"
+        assert int(slave.RDATA.value) == read_data, "Read data must fold back to slave"
+        assert int(slave.RRESP.value) == 0, "Read response should indicate success"
+
+        slave.ARVALID.value = 0
+        slave.RREADY.value = 0
+        _set_value(entry["inputs"]["RVALID"], index, 0)
+        _set_value(entry["inputs"]["RDATA"], index, 0)
+        await Timer(1, units="ns")

tests/cocotb/axi4lite/smoke/test_runner.py

@@ -0,0 +1,59 @@
+"""Pytest wrapper launching the AXI4-Lite cocotb smoke tests."""
+
+from __future__ import annotations
+
+import json
+from pathlib import Path
+
+import pytest
+
+from peakrdl_busdecoder.cpuif.axi4lite.axi4_lite_cpuif_flat import AXI4LiteCpuifFlat
+
+try:  # pragma: no cover - optional dependency shim
+    from cocotb.runner import get_runner
+except ImportError:  # pragma: no cover
+    from cocotb_tools.runner import get_runner
+
+from tests.cocotb_lib import RDL_CASES
+from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
+def test_axi4lite_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
+    """Compile each AXI4-Lite design variant and execute the cocotb smoke test."""
+    repo_root = Path(__file__).resolve().parents[4]
+    rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
+    build_root = tmp_path / top_name
+
+    module_path, package_path, config = prepare_cpuif_case(
+        str(rdl_path),
+        top_name,
+        build_root,
+        cpuif_cls=AXI4LiteCpuifFlat,
+        control_signal="AWVALID",
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "axi4lite_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    sim_build = build_root / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=sim_build,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.axi4lite.smoke.test_register_access",
+        build_dir=sim_build,
+        log_file=str(build_root / "simulation.log"),
+        extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
+    )

tests/cocotb/axi4lite/smoke/test_variable_depth.py

@@ -0,0 +1,271 @@
+"""AXI4-Lite smoke tests for variable depth design testing max_decode_depth parameter."""
+
+import cocotb
+from cocotb.triggers import Timer
+
+
+class _AxilSlaveShim:
+    def __init__(self, dut):
+        prefix = "s_axil"
+        self.AWREADY = getattr(dut, f"{prefix}_AWREADY")
+        self.AWVALID = getattr(dut, f"{prefix}_AWVALID")
+        self.AWADDR = getattr(dut, f"{prefix}_AWADDR")
+        self.AWPROT = getattr(dut, f"{prefix}_AWPROT")
+        self.WREADY = getattr(dut, f"{prefix}_WREADY")
+        self.WVALID = getattr(dut, f"{prefix}_WVALID")
+        self.WDATA = getattr(dut, f"{prefix}_WDATA")
+        self.WSTRB = getattr(dut, f"{prefix}_WSTRB")
+        self.BREADY = getattr(dut, f"{prefix}_BREADY")
+        self.BVALID = getattr(dut, f"{prefix}_BVALID")
+        self.BRESP = getattr(dut, f"{prefix}_BRESP")
+        self.ARREADY = getattr(dut, f"{prefix}_ARREADY")
+        self.ARVALID = getattr(dut, f"{prefix}_ARVALID")
+        self.ARADDR = getattr(dut, f"{prefix}_ARADDR")
+        self.ARPROT = getattr(dut, f"{prefix}_ARPROT")
+        self.RREADY = getattr(dut, f"{prefix}_RREADY")
+        self.RVALID = getattr(dut, f"{prefix}_RVALID")
+        self.RDATA = getattr(dut, f"{prefix}_RDATA")
+        self.RRESP = getattr(dut, f"{prefix}_RRESP")
+
+
+class _AxilMasterShim:
+    def __init__(self, dut, base: str):
+        self.AWREADY = getattr(dut, f"{base}_AWREADY")
+        self.AWVALID = getattr(dut, f"{base}_AWVALID")
+        self.AWADDR = getattr(dut, f"{base}_AWADDR")
+        self.AWPROT = getattr(dut, f"{base}_AWPROT")
+        self.WREADY = getattr(dut, f"{base}_WREADY")
+        self.WVALID = getattr(dut, f"{base}_WVALID")
+        self.WDATA = getattr(dut, f"{base}_WDATA")
+        self.WSTRB = getattr(dut, f"{base}_WSTRB")
+        self.BREADY = getattr(dut, f"{base}_BREADY")
+        self.BVALID = getattr(dut, f"{base}_BVALID")
+        self.BRESP = getattr(dut, f"{base}_BRESP")
+        self.ARREADY = getattr(dut, f"{base}_ARREADY")
+        self.ARVALID = getattr(dut, f"{base}_ARVALID")
+        self.ARADDR = getattr(dut, f"{base}_ARADDR")
+        self.ARPROT = getattr(dut, f"{base}_ARPROT")
+        self.RREADY = getattr(dut, f"{base}_RREADY")
+        self.RVALID = getattr(dut, f"{base}_RVALID")
+        self.RDATA = getattr(dut, f"{base}_RDATA")
+        self.RRESP = getattr(dut, f"{base}_RRESP")
+
+
+def _axil_slave(dut):
+    return getattr(dut, "s_axil", None) or _AxilSlaveShim(dut)
+
+
+def _axil_master(dut, base: str):
+    return getattr(dut, base, None) or _AxilMasterShim(dut, base)
+
+
+@cocotb.test()
+async def test_depth_1(dut):
+    """Test max_decode_depth=1 - should have interface for inner1 only."""
+    s_axil = _axil_slave(dut)
+    
+    # At depth 1, we should have m_axil_inner1 but not deeper interfaces
+    inner1 = _axil_master(dut, "m_axil_inner1")
+    
+    # Default slave side inputs
+    s_axil.AWVALID.value = 0
+    s_axil.AWADDR.value = 0
+    s_axil.AWPROT.value = 0
+    s_axil.WVALID.value = 0
+    s_axil.WDATA.value = 0
+    s_axil.WSTRB.value = 0
+    s_axil.BREADY.value = 0
+    s_axil.ARVALID.value = 0
+    s_axil.ARADDR.value = 0
+    s_axil.ARPROT.value = 0
+    s_axil.RREADY.value = 0
+    
+    inner1.AWREADY.value = 0
+    inner1.WREADY.value = 0
+    inner1.BVALID.value = 0
+    inner1.BRESP.value = 0
+    inner1.ARREADY.value = 0
+    inner1.RVALID.value = 0
+    inner1.RDATA.value = 0
+    inner1.RRESP.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select inner1)
+    inner1.AWREADY.value = 1
+    inner1.WREADY.value = 1
+    s_axil.AWVALID.value = 1
+    s_axil.AWADDR.value = 0x0
+    s_axil.WVALID.value = 1
+    s_axil.WDATA.value = 0x12345678
+    s_axil.WSTRB.value = 0xF
+    
+    await Timer(1, units="ns")
+    
+    assert int(inner1.AWVALID.value) == 1, "inner1 write address valid must be set"
+    assert int(inner1.WVALID.value) == 1, "inner1 write data valid must be set"
+
+
+@cocotb.test()
+async def test_depth_2(dut):
+    """Test max_decode_depth=2 - should have interfaces for reg1 and inner2."""
+    s_axil = _axil_slave(dut)
+    
+    # At depth 2, we should have m_axil_reg1 and m_axil_inner2
+    reg1 = _axil_master(dut, "m_axil_reg1")
+    inner2 = _axil_master(dut, "m_axil_inner2")
+    
+    # Default slave side inputs
+    s_axil.AWVALID.value = 0
+    s_axil.AWADDR.value = 0
+    s_axil.AWPROT.value = 0
+    s_axil.WVALID.value = 0
+    s_axil.WDATA.value = 0
+    s_axil.WSTRB.value = 0
+    s_axil.BREADY.value = 0
+    s_axil.ARVALID.value = 0
+    s_axil.ARADDR.value = 0
+    s_axil.ARPROT.value = 0
+    s_axil.RREADY.value = 0
+    
+    for master in [reg1, inner2]:
+        master.AWREADY.value = 0
+        master.WREADY.value = 0
+        master.BVALID.value = 0
+        master.BRESP.value = 0
+        master.ARREADY.value = 0
+        master.RVALID.value = 0
+        master.RDATA.value = 0
+        master.RRESP.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select reg1)
+    reg1.AWREADY.value = 1
+    reg1.WREADY.value = 1
+    s_axil.AWVALID.value = 1
+    s_axil.AWADDR.value = 0x0
+    s_axil.WVALID.value = 1
+    s_axil.WDATA.value = 0xABCDEF01
+    s_axil.WSTRB.value = 0xF
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
+    assert int(inner2.AWVALID.value) == 0, "inner2 should not be selected"
+    
+    # Reset
+    s_axil.AWVALID.value = 0
+    s_axil.WVALID.value = 0
+    reg1.AWREADY.value = 0
+    reg1.WREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x10 (should select inner2)
+    inner2.AWREADY.value = 1
+    inner2.WREADY.value = 1
+    s_axil.AWVALID.value = 1
+    s_axil.AWADDR.value = 0x10
+    s_axil.WVALID.value = 1
+    s_axil.WDATA.value = 0x23456789
+    s_axil.WSTRB.value = 0xF
+    
+    await Timer(1, units="ns")
+    
+    assert int(inner2.AWVALID.value) == 1, "inner2 must be selected for address 0x10"
+    assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
+
+
+@cocotb.test()
+async def test_depth_0(dut):
+    """Test max_decode_depth=0 - should have interfaces for all leaf registers."""
+    s_axil = _axil_slave(dut)
+    
+    # At depth 0, we should have all leaf registers: reg1, reg2, reg2b
+    reg1 = _axil_master(dut, "m_axil_reg1")
+    reg2 = _axil_master(dut, "m_axil_reg2")
+    reg2b = _axil_master(dut, "m_axil_reg2b")
+    
+    # Default slave side inputs
+    s_axil.AWVALID.value = 0
+    s_axil.AWADDR.value = 0
+    s_axil.AWPROT.value = 0
+    s_axil.WVALID.value = 0
+    s_axil.WDATA.value = 0
+    s_axil.WSTRB.value = 0
+    s_axil.BREADY.value = 0
+    s_axil.ARVALID.value = 0
+    s_axil.ARADDR.value = 0
+    s_axil.ARPROT.value = 0
+    s_axil.RREADY.value = 0
+    
+    for master in [reg1, reg2, reg2b]:
+        master.AWREADY.value = 0
+        master.WREADY.value = 0
+        master.BVALID.value = 0
+        master.BRESP.value = 0
+        master.ARREADY.value = 0
+        master.RVALID.value = 0
+        master.RDATA.value = 0
+        master.RRESP.value = 0
+    
+    await Timer(1, units="ns")
+    
+    # Write to address 0x0 (should select reg1)
+    reg1.AWREADY.value = 1
+    reg1.WREADY.value = 1
+    s_axil.AWVALID.value = 1
+    s_axil.AWADDR.value = 0x0
+    s_axil.WVALID.value = 1
+    s_axil.WDATA.value = 0x11111111
+    s_axil.WSTRB.value = 0xF
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg1.AWVALID.value) == 1, "reg1 must be selected for address 0x0"
+    assert int(reg2.AWVALID.value) == 0, "reg2 should not be selected"
+    assert int(reg2b.AWVALID.value) == 0, "reg2b should not be selected"
+    
+    # Reset
+    s_axil.AWVALID.value = 0
+    s_axil.WVALID.value = 0
+    reg1.AWREADY.value = 0
+    reg1.WREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x10 (should select reg2)
+    reg2.AWREADY.value = 1
+    reg2.WREADY.value = 1
+    s_axil.AWVALID.value = 1
+    s_axil.AWADDR.value = 0x10
+    s_axil.WVALID.value = 1
+    s_axil.WDATA.value = 0x22222222
+    s_axil.WSTRB.value = 0xF
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg2.AWVALID.value) == 1, "reg2 must be selected for address 0x10"
+    assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
+    assert int(reg2b.AWVALID.value) == 0, "reg2b should not be selected"
+    
+    # Reset
+    s_axil.AWVALID.value = 0
+    s_axil.WVALID.value = 0
+    reg2.AWREADY.value = 0
+    reg2.WREADY.value = 0
+    await Timer(1, units="ns")
+    
+    # Write to address 0x14 (should select reg2b)
+    reg2b.AWREADY.value = 1
+    reg2b.WREADY.value = 1
+    s_axil.AWVALID.value = 1
+    s_axil.AWADDR.value = 0x14
+    s_axil.WVALID.value = 1
+    s_axil.WDATA.value = 0x33333333
+    s_axil.WSTRB.value = 0xF
+    
+    await Timer(1, units="ns")
+    
+    assert int(reg2b.AWVALID.value) == 1, "reg2b must be selected for address 0x14"
+    assert int(reg1.AWVALID.value) == 0, "reg1 should not be selected"
+    assert int(reg2.AWVALID.value) == 0, "reg2 should not be selected"

tests/cocotb/axi4lite/smoke/test_variable_depth_runner.py

@@ -0,0 +1,128 @@
+"""Pytest wrapper launching the AXI4-Lite cocotb smoke test for variable depth."""
+
+from pathlib import Path
+
+import pytest
+
+from peakrdl_busdecoder.cpuif.axi4lite.axi4_lite_cpuif_flat import AXI4LiteCpuifFlat
+
+try:  # pragma: no cover - optional dependency shim
+    from cocotb.runner import get_runner
+except ImportError:  # pragma: no cover
+    from cocotb_tools.runner import get_runner
+
+from tests.cocotb_lib.utils import compile_rdl_and_export, get_verilog_sources
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_axi4lite_variable_depth_1(tmp_path: Path) -> None:
+    """Test AXI4-Lite design with max_decode_depth=1."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=AXI4LiteCpuifFlat,
+        max_decode_depth=1,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "axi4lite_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.axi4lite.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth1.log"),
+        testcase="test_depth_1",
+    )
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_axi4lite_variable_depth_2(tmp_path: Path) -> None:
+    """Test AXI4-Lite design with max_decode_depth=2."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=AXI4LiteCpuifFlat,
+        max_decode_depth=2,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "axi4lite_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.axi4lite.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth2.log"),
+        testcase="test_depth_2",
+    )
+
+
+@pytest.mark.simulation
+@pytest.mark.verilator
+def test_axi4lite_variable_depth_0(tmp_path: Path) -> None:
+    """Test AXI4-Lite design with max_decode_depth=0 (all levels)."""
+    repo_root = Path(__file__).resolve().parents[4]
+
+    module_path, package_path = compile_rdl_and_export(
+        str(repo_root / "tests" / "cocotb_lib" / "variable_depth.rdl"),
+        "variable_depth",
+        tmp_path,
+        cpuif_cls=AXI4LiteCpuifFlat,
+        max_decode_depth=0,
+    )
+
+    sources = get_verilog_sources(
+        module_path,
+        package_path,
+        [repo_root / "hdl-src" / "axi4lite_intf.sv"],
+    )
+
+    runner = get_runner("verilator")
+    build_dir = tmp_path / "sim_build"
+
+    runner.build(
+        sources=sources,
+        hdl_toplevel=module_path.stem,
+        build_dir=build_dir,
+    )
+
+    runner.test(
+        hdl_toplevel=module_path.stem,
+        test_module="tests.cocotb.axi4lite.smoke.test_variable_depth",
+        build_dir=build_dir,
+        log_file=str(tmp_path / "sim_depth0.log"),
+        testcase="test_depth_0",
+    )

tests/cocotb_lib/__init__.py

@@ -0,0 +1,10 @@
+"""Manifest of SystemRDL sources used by the cocotb simulations."""
+
+RDL_CASES: list[tuple[str, str]] = [
+    ("simple.rdl", "simple_test"),
+    ("multiple_reg.rdl", "multi_reg"),
+    ("deep_hierarchy.rdl", "deep_hierarchy"),
+    ("wide_status.rdl", "wide_status"),
+    ("variable_layout.rdl", "variable_layout"),
+    ("asymmetric_bus.rdl", "asymmetric_bus"),
+]

tests/cocotb_lib/handle_utils.py

@@ -0,0 +1,69 @@
+"""Utilities for resolving cocotb signal handles across simulators."""
+
+from __future__ import annotations
+
+from typing import Any, Iterable
+
+
+class SignalHandle:
+    """
+    Wrapper that resolves array elements even when the simulator does not expose
+    unpacked arrays through ``handle[idx]``.
+    """
+
+    def __init__(self, dut, name: str) -> None:
+        self._dut = dut
+        self._name = name
+        self._base = getattr(dut, name, None)
+        self._cache: dict[tuple[int, ...], Any] = {}
+
+    def resolve(self, indices: tuple[int, ...]):
+        if not indices:
+            return self._base if self._base is not None else self._lookup(tuple())
+
+        if indices not in self._cache:
+            self._cache[indices] = self._direct_or_lookup(indices)
+        return self._cache[indices]
+
+    def _direct_or_lookup(self, indices: tuple[int, ...]):
+        if self._base is not None:
+            ref = self._base
+            try:
+                for idx in indices:
+                    ref = ref[idx]
+                return ref
+            except (IndexError, TypeError, AttributeError):
+                pass
+
+        return self._lookup(indices)
+
+    def _lookup(self, indices: tuple[int, ...]):
+        suffix = "".join(f"[{idx}]" for idx in indices)
+        path = f"{self._name}{suffix}"
+
+        try:
+            return getattr(self._dut, path)
+        except AttributeError:
+            pass
+
+        errors: list[Exception] = []
+        for extended in (False, True):
+            try:
+                return self._dut._id(path, extended=extended)
+            except (AttributeError, ValueError) as exc:
+                errors.append(exc)
+
+        raise AttributeError(f"Unable to resolve handle '{path}' via dut._id") from errors[-1]
+
+
+def resolve_handle(handle, indices: Iterable[int]):
+    """Resolve either a regular cocotb handle or a ``SignalHandle`` wrapper."""
+    index_tuple = tuple(indices)
+
+    if isinstance(handle, SignalHandle):
+        return handle.resolve(index_tuple)
+
+    ref = handle
+    for idx in index_tuple:
+        ref = ref[idx]
+    return ref

tests/cocotb_lib/rdl/asymmetric_bus.rdl

@@ -0,0 +1,105 @@
+regfile port_rf {
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } port_enable[0:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } port_speed[3:1];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } port_width[8:4];
+    } control @ 0x0;
+
+    reg {
+        field {
+            sw = r;
+            hw = w;
+            reset = 0x0;
+        } error_count[15:0];
+
+        field {
+            sw = r;
+            hw = w;
+            reset = 0x0;
+        } retry_count[31:16];
+    } counters @ 0x4;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } qos[7:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } virtual_channel[9:8];
+    } qos @ 0x8;
+};
+
+addrmap asymmetric_bus {
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } control[3:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } id[15:4];
+    } control @ 0x0;
+
+    reg {
+        field {
+            sw = r;
+            hw = w;
+            reset = 0x0;
+        } status_flags[19:0];
+    } status @ 0x4;
+
+    reg {
+        regwidth = 64;
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x00abcdef;
+        } timestamp_low[31:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x00123456;
+        } timestamp_high[55:32];
+    } timestamp @ 0x8;
+
+    reg {
+        regwidth = 128;
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } extended_id[63:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x1;
+        } parity[64:64];
+    } extended @ 0x10;
+
+    port_rf port[6] @ 0x40 += 0x20;
+};

tests/cocotb_lib/rdl/deep_hierarchy.rdl

@@ -0,0 +1,115 @@
+addrmap deep_hierarchy {
+    regfile context_rf {
+        reg {
+            field {
+                sw = rw;
+                hw = r;
+                reset = 0x1;
+            } enable[7:0];
+
+            field {
+                sw = r;
+                hw = w;
+                onread = rclr;
+                reset = 0x0;
+            } status[15:8];
+
+            field {
+                sw = rw;
+                hw = rw;
+                reset = 0x55;
+            } mode[23:16];
+        } command @ 0x0;
+
+        reg {
+            field {
+                sw = rw;
+                hw = rw;
+                reset = 0x1234;
+            } threshold[15:0];
+        } threshold @ 0x4;
+
+        reg {
+            field {
+                sw = rw;
+                hw = rw;
+                reset = 0x0;
+            } counter[31:0];
+        } counter @ 0x8;
+    };
+
+    regfile engine_rf {
+        context_rf context[3] @ 0x0;
+
+        reg {
+            field {
+                sw = rw;
+                hw = rw;
+                reset = 0x0;
+            } timeout[15:0];
+
+            field {
+                sw = rw;
+                hw = rw;
+                reset = 0x1;
+            } priority[19:16];
+        } config @ 0x30;
+
+        reg {
+            field {
+                sw = r;
+                hw = w;
+                onread = rclr;
+                reset = 0x0;
+            } error[31:0];
+        } error_log @ 0x34;
+    };
+
+    addrmap fabric_slice {
+        engine_rf engines[4] @ 0x0;
+
+        regfile monitor_rf {
+            reg {
+                field {
+                    sw = r;
+                    hw = w;
+                    reset = 0x0;
+                } perf_count[31:0];
+            } perf @ 0x0;
+
+            reg {
+                field {
+                    sw = r;
+                    hw = w;
+                    reset = 0x0;
+                } last_error[31:0];
+            } last_error @ 0x4;
+        };
+
+        monitor_rf monitor @ 0x400;
+
+        reg {
+            field {
+                sw = rw;
+                hw = rw;
+                reset = 0xdeadbeef;
+            } fabric_ctrl[31:0];
+        } fabric_ctrl @ 0x500;
+    };
+
+    fabric_slice slices[2] @ 0x0 += 0x800;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x1;
+        } global_enable[0:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x4;
+        } debug_level[3:1];
+    } global_control @ 0x1000;
+};

tests/cocotb_lib/rdl/multiple_reg.rdl

@@ -0,0 +1,22 @@
+addrmap multi_reg {
+    reg {
+        field {
+            sw=rw;
+            hw=r;
+        } data[31:0];
+    } reg1 @ 0x0;
+
+    reg {
+        field {
+            sw=r;
+            hw=w;
+        } status[15:0];
+    } reg2 @ 0x4;
+
+    reg {
+        field {
+            sw=rw;
+            hw=r;
+        } control[7:0];
+    } reg3 @ 0x8;
+};

tests/cocotb_lib/rdl/simple.rdl

@@ -0,0 +1,8 @@
+addrmap simple_test {
+    reg {
+        field {
+            sw=rw;
+            hw=r;
+        } data[31:0];
+    } test_reg @ 0x0;
+};

tests/cocotb_lib/rdl/variable_layout.rdl

@@ -0,0 +1,156 @@
+reg ctrl_reg_t {
+    desc = "Control register shared across channels.";
+
+    field {
+        sw = rw;
+        hw = rw;
+        reset = 0x1;
+    } enable[0:0];
+
+    field {
+        sw = rw;
+        hw = rw;
+        reset = 0x2;
+    } mode[3:1];
+
+    field {
+        sw = rw;
+        hw = rw;
+        reset = 0x0;
+    } prescale[11:4];
+};
+
+regfile channel_rf {
+    ctrl_reg_t control @ 0x0;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } gain[11:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x200;
+        } offset[23:12];
+    } calibrate @ 0x4;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } sample_count[15:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } error_count[31:16];
+    } counters @ 0x8;
+};
+
+regfile slice_rf {
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } slope[15:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } intercept[31:16];
+    } calibration @ 0x0;
+
+    reg {
+        regwidth = 64;
+        field {
+            sw = r;
+            hw = w;
+            reset = 0x0;
+        } min_val[31:0];
+
+        field {
+            sw = r;
+            hw = w;
+            reset = 0x0;
+        } max_val[63:32];
+    } range @ 0x4;
+};
+
+regfile tile_rf {
+    channel_rf channel[3] @ 0x0;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } tile_mode[1:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } tile_enable[2:2];
+    } tile_ctrl @ 0x100;
+
+    slice_rf slice[2] @ 0x200;
+};
+
+regfile summary_rf {
+    reg {
+        field {
+            sw = r;
+            hw = w;
+            reset = 0x0;
+        } total_errors[31:0];
+    } errors @ 0x0;
+
+    reg {
+        field {
+            sw = r;
+            hw = w;
+            reset = 0x0;
+        } total_samples[31:0];
+    } samples @ 0x4;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } interrupt_enable[7:0];
+    } interrupt_enable @ 0x8;
+};
+
+addrmap variable_layout {
+    tile_rf tiles[2] @ 0x0;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } watchdog_enable[0:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x100;
+        } watchdog_timeout[16:1];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } watchdog_mode[18:17];
+    } watchdog @ 0x2000;
+
+    summary_rf summary @ 0x3000;
+};

tests/cocotb_lib/rdl/wide_status.rdl

@@ -0,0 +1,69 @@
+reg status_reg_t {
+    regwidth = 64;
+    desc = "Status register capturing wide flags and sticky bits.";
+
+    field {
+        sw = r;
+        hw = w;
+        onread = rclr;
+        reset = 0x0;
+    } flags[62:0];
+
+    field {
+        sw = rw;
+        hw = r;
+        reset = 0x1;
+    } sticky_bit[63:63];
+};
+
+reg metrics_reg_t {
+    regwidth = 64;
+    desc = "Metrics register pairing counters with thresholds.";
+
+    field {
+        sw = r;
+        hw = w;
+        reset = 0x0;
+    } count[31:0];
+
+    field {
+        sw = rw;
+        hw = rw;
+        reset = 0x0;
+    } threshold[63:32];
+};
+
+addrmap wide_status {
+    status_reg_t status_blocks[16] @ 0x0;
+
+    metrics_reg_t metrics[4] @ 0x400;
+
+    reg {
+        regwidth = 128;
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } configuration[127:0];
+    } configuration @ 0x800;
+
+    reg {
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0;
+        } version_major[7:0];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x1;
+        } version_minor[15:8];
+
+        field {
+            sw = rw;
+            hw = rw;
+            reset = 0x0100;
+        } build[31:16];
+    } version @ 0x900;
+};

tests/cocotb_lib/utils.py

@@ -0,0 +1,274 @@
+"""Common utilities for cocotb testbenches."""
+
+from __future__ import annotations
+
+from collections import defaultdict
+from pathlib import Path
+from typing import Any
+
+from systemrdl import RDLCompiler
+from systemrdl.node import AddressableNode, AddrmapNode, RegNode
+
+from peakrdl_busdecoder.cpuif.base_cpuif import BaseCpuif
+from peakrdl_busdecoder.exporter import BusDecoderExporter
+
+
+def compile_rdl_and_export(
+    rdl_source: str, top_name: str, output_dir: Path, cpuif_cls: type[BaseCpuif], **kwargs: Any
+) -> tuple[Path, Path]:
+    """
+    Compile RDL source and export to SystemVerilog.
+
+    Args:
+        rdl_source: SystemRDL source code path
+        top_name: Name of the top-level addrmap
+        output_dir: Directory to write generated files
+        cpuif_cls: CPU interface class to use
+        **kwargs: Additional arguments to pass to exporter
+
+    Returns:
+        Tuple of (module_path, package_path) for generated files
+    """
+    # Compile RDL source
+    compiler = RDLCompiler()
+
+    compiler.compile_file(rdl_source)
+    top = compiler.elaborate(top_name)
+
+    # Export to SystemVerilog
+    exporter = BusDecoderExporter()
+    exporter.export(top, str(output_dir), cpuif_cls=cpuif_cls, **kwargs)
+
+    # Return paths to generated files
+    module_name = kwargs.get("module_name", top_name)
+    package_name = kwargs.get("package_name", f"{top_name}_pkg")
+
+    module_path = Path(output_dir) / f"{module_name}.sv"
+    package_path = Path(output_dir) / f"{package_name}.sv"
+
+    return module_path, package_path
+
+
+def get_verilog_sources(module_path: Path, package_path: Path, intf_files: list[Path]) -> list[str]:
+    """
+    Get list of Verilog source files needed for simulation.
+
+    Args:
+        module_path: Path to the generated module file
+        package_path: Path to the generated package file
+        intf_files: List of paths to interface definition files
+
+    Returns:
+        List of source file paths as strings
+    """
+    sources = []
+    # Add interface files first
+    sources.extend([str(f) for f in intf_files])
+    # Add package file
+    sources.append(str(package_path))
+    # Add module file
+    sources.append(str(module_path))
+    return sources
+
+
+def prepare_cpuif_case(
+    rdl_source: str,
+    top_name: str,
+    output_dir: Path,
+    cpuif_cls: type[BaseCpuif],
+    *,
+    control_signal: str,
+    max_samples_per_master: int = 3,
+    exporter_kwargs: dict[str, Any] | None = None,
+) -> tuple[Path, Path, dict[str, Any]]:
+    """
+    Compile SystemRDL, export the CPUIF, and build a configuration payload for cocotb tests.
+
+    Parameters
+    ----------
+    rdl_source:
+        Path to the SystemRDL source file.
+    top_name:
+        Name of the top-level addrmap to elaborate.
+    output_dir:
+        Directory where generated HDL will be written.
+    cpuif_cls:
+        CPUIF implementation class to use during export.
+    control_signal:
+        Name of the control signal used to identify master ports
+        (``"PSEL"`` for APB, ``"AWVALID"`` for AXI4-Lite, etc.).
+    max_samples_per_master:
+        Limit for the number of register addresses sampled per master in the test matrix.
+    exporter_kwargs:
+        Optional keyword overrides passed through to :class:`BusDecoderExporter`.
+
+    Returns
+    -------
+    tuple
+        ``(module_path, package_path, config_dict)``, where the configuration dictionary
+        is JSON-serializable and describes masters, indices, and sampled transactions.
+    """
+    compiler = RDLCompiler()
+    compiler.compile_file(rdl_source)
+    root = compiler.elaborate(top_name)
+    top_node = root.top  # type: ignore[assignment]
+
+    export_kwargs: dict[str, Any] = {"cpuif_cls": cpuif_cls}
+    if exporter_kwargs:
+        export_kwargs.update(exporter_kwargs)
+
+    exporter = BusDecoderExporter()
+    exporter.export(root, str(output_dir), **export_kwargs)
+
+    module_name = export_kwargs.get("module_name", top_name)
+    package_name = export_kwargs.get("package_name", f"{top_name}_pkg")
+
+    module_path = Path(output_dir) / f"{module_name}.sv"
+    package_path = Path(output_dir) / f"{package_name}.sv"
+
+    config = _build_case_config(
+        top_node,
+        exporter.cpuif,
+        control_signal,
+        max_samples_per_master=max_samples_per_master,
+    )
+
+    config["address_width"] = exporter.cpuif.addr_width
+    config["data_width"] = exporter.cpuif.data_width
+    config["byte_width"] = exporter.cpuif.data_width // 8
+
+    return module_path, package_path, config
+
+
+def _build_case_config(
+    top_node: AddrmapNode,
+    cpuif: BaseCpuif,
+    control_signal: str,
+    *,
+    max_samples_per_master: int,
+) -> dict[str, Any]:
+    master_entries: dict[str, dict[str, Any]] = {}
+
+    for child in cpuif.addressable_children:
+        signal = cpuif.signal(control_signal, child)
+        # Example: m_apb_tiles_PSEL[N_TILESS] -> m_apb_tiles
+        base = signal.split("[", 1)[0]
+        suffix = f"_{control_signal}"
+        if not base.endswith(suffix):
+            raise ValueError(f"Unable to derive port prefix from '{signal}'")
+        port_prefix = base[: -len(suffix)]
+
+        master_entries[child.inst_name] = {
+            "inst_name": child.inst_name,
+            "port_prefix": port_prefix,
+            "is_array": bool(child.is_array),
+            "dimensions": list(child.array_dimensions or []),
+            "indices": set(),
+        }
+
+    # Map each register to its top-level master and collect addresses
+    groups: dict[tuple[str, tuple[int, ...]], list[tuple[int, str]]] = defaultdict(list)
+
+    def visit(node: AddressableNode) -> None:
+        if isinstance(node, RegNode):
+            master = node  # type: AddressableNode
+            while master.parent is not top_node:
+                parent = master.parent
+                if not isinstance(parent, AddressableNode):
+                    raise RuntimeError("Encountered unexpected hierarchy while resolving master node")
+                master = parent
+
+            inst_name = master.inst_name
+            if inst_name not in master_entries:
+                # Handles cases where the register itself is the master (direct child of top)
+                signal = cpuif.signal(control_signal, master)
+                base = signal.split("[", 1)[0]
+                suffix = f"_{control_signal}"
+                if not base.endswith(suffix):
+                    raise ValueError(f"Unable to derive port prefix from '{signal}'")
+                port_prefix = base[: -len(suffix)]
+                master_entries[inst_name] = {
+                    "inst_name": inst_name,
+                    "port_prefix": port_prefix,
+                    "is_array": bool(master.is_array),
+                    "dimensions": list(master.array_dimensions or []),
+                    "indices": set(),
+                }
+
+            idx_tuple = tuple(master.current_idx or [])
+            master_entries[inst_name]["indices"].add(idx_tuple)
+
+            relative_addr = int(node.absolute_address) - int(top_node.absolute_address)
+            full_path = node.get_path()
+            label = full_path.split(".", 1)[1] if "." in full_path else full_path
+            groups[(inst_name, idx_tuple)].append((relative_addr, label))
+
+        for child in node.children(unroll=True):
+            if isinstance(child, AddressableNode):
+                visit(child)
+
+    visit(top_node)
+
+    masters_list = []
+    for entry in master_entries.values():
+        indices = entry["indices"] or {()}
+        entry["indices"] = [list(idx) for idx in sorted(indices)]
+        masters_list.append(
+            {
+                "inst_name": entry["inst_name"],
+                "port_prefix": entry["port_prefix"],
+                "is_array": entry["is_array"],
+                "dimensions": entry["dimensions"],
+                "indices": entry["indices"],
+            }
+        )
+
+    transactions = []
+    for (inst_name, idx_tuple), items in groups.items():
+        addresses = sorted({addr for addr, _ in items})
+        samples = _sample_addresses(addresses, max_samples_per_master)
+        for addr in samples:
+            label = next(lbl for candidate, lbl in items if candidate == addr)
+            transactions.append(
+                {
+                    "address": addr,
+                    "master": inst_name,
+                    "index": list(idx_tuple),
+                    "label": label,
+                }
+            )
+
+    transactions.sort(key=lambda item: (item["master"], item["index"], item["address"]))
+
+    masters_list.sort(key=lambda item: item["inst_name"])
+
+    return {
+        "masters": masters_list,
+        "transactions": transactions,
+    }
+
+
+def _sample_addresses(addresses: list[int], max_samples: int) -> list[int]:
+    if len(addresses) <= max_samples:
+        return addresses
+
+    samples: list[int] = []
+    samples.append(addresses[0])
+    if len(addresses) > 1:
+        samples.append(addresses[-1])
+
+    if len(addresses) > 2:
+        mid = addresses[len(addresses) // 2]
+        if mid not in samples:
+            samples.append(mid)
+
+    idx = 1
+    while len(samples) < max_samples:
+        pos = (len(addresses) * idx) // max_samples
+        candidate = addresses[min(pos, len(addresses) - 1)]
+        if candidate not in samples:
+            samples.append(candidate)
+        idx += 1
+
+    samples.sort()
+    return samples

tests/cocotb_lib/variable_depth.rdl

@@ -0,0 +1,31 @@
+// Variable depth register hierarchy for testing max_decode_depth parameter
+addrmap level2 {
+    reg {
+        field {
+            sw=rw;
+            hw=r;
+        } data2[31:0];
+    } reg2 @ 0x0;
+    
+    reg {
+        field {
+            sw=rw;
+            hw=r;
+        } data2b[31:0];
+    } reg2b @ 0x4;
+};
+
+addrmap level1 {
+    reg {
+        field {
+            sw=rw;
+            hw=r;
+        } data1[31:0];
+    } reg1 @ 0x0;
+    
+    level2 inner2 @ 0x10;
+};
+
+addrmap variable_depth {
+    level1 inner1 @ 0x0;
+};

tests/conftest.py

@@ -0,0 +1,60 @@
+"""Pytest fixtures for unit tests."""
+
+from __future__ import annotations
+
+collect_ignore_glob = ["cocotb/*/smoke/test_register_access.py", "cocotb/*/smoke/test_variable_depth.py"]
+
+import os
+from collections.abc import Callable
+from pathlib import Path
+from tempfile import NamedTemporaryFile
+
+import pytest
+from systemrdl import RDLCompileError, RDLCompiler  # type:ignore
+from systemrdl.node import AddrmapNode
+
+_SHIM_DIR = Path(__file__).resolve().parents[1] / "tools" / "shims"
+os.environ["PATH"] = f"{_SHIM_DIR}{os.pathsep}{os.environ.get('PATH', '')}"
+
+
+@pytest.fixture
+def compile_rdl(tmp_path: Path) -> Callable[..., AddrmapNode]:
+    """Compile inline SystemRDL source and return the elaborated root node.
+
+    Parameters
+    ----------
+    tmp_path:
+        Temporary directory provided by pytest.
+    """
+
+    def _compile(
+        source: str,
+        *,
+        top: str | None = None,
+        defines: dict[str, str] | None = None,
+        include_paths: list[Path | str] | None = None,
+    ) -> AddrmapNode:
+        compiler = RDLCompiler()
+        # Use delete=False to keep the file around after closing
+        with NamedTemporaryFile("w", suffix=".rdl", dir=tmp_path, delete=False) as tmp_file:
+            tmp_file.write(source)
+            tmp_file.flush()
+
+            try:
+                compiler.compile_file(
+                    tmp_file.name,
+                    incl_search_paths=(list(map(str, include_paths)) if include_paths else None),
+                    defines=defines,
+                )
+                if top is not None:
+                    root = compiler.elaborate(top)  # type:ignore
+                    return root.top
+                root = compiler.elaborate()  # type:ignore
+                return root.top
+            except RDLCompileError:
+                # Print error messages if available
+                if hasattr(compiler, "print_messages"):
+                    compiler.print_messages()  # type:ignore
+                raise
+
+    return _compile

tests/exporter/test_bus_decoder_exporter.py

@@ -1,20 +1,16 @@
-"""Integration tests for the BusDecoderExporter."""
+from collections.abc import Callable
-
-from __future__ import annotations
-
-import os
 from pathlib import Path
 
-import pytest
+from systemrdl.node import AddrmapNode
 
+from peakrdl_busdecoder import BusDecoderExporter
 from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
-from peakrdl_busdecoder.exporter import BusDecoderExporter
 
 
 class TestBusDecoderExporter:
     """Test the top-level BusDecoderExporter."""
 
-    def test_simple_register_export(self, compile_rdl, tmp_path):
+    def test_simple_register_export(self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path) -> None:
         """Test exporting a simple register."""
         rdl_source = """
         addrmap simple_reg {
@@ -47,7 +43,7 @@ class TestBusDecoderExporter:
         package_content = package_file.read_text()
         assert "package simple_reg_pkg" in package_content
 
-    def test_register_array_export(self, compile_rdl, tmp_path):
+    def test_register_array_export(self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path) -> None:
         """Test exporting a register array."""
         rdl_source = """
         addrmap reg_array {
@@ -73,7 +69,7 @@ class TestBusDecoderExporter:
         assert "module reg_array" in module_content
         assert "my_regs" in module_content
 
-    def test_nested_addrmap_export(self, compile_rdl, tmp_path):
+    def test_nested_addrmap_export(self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path) -> None:
         """Test exporting nested addrmaps."""
         rdl_source = """
         addrmap inner_block {
@@ -93,7 +89,8 @@ class TestBusDecoderExporter:
 
         exporter = BusDecoderExporter()
         output_dir = str(tmp_path)
-        exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
+        # Use depth=0 to descend all the way to registers
+        exporter.export(top, output_dir, cpuif_cls=APB4Cpuif, max_decode_depth=0)
 
         # Check that output files are created
         module_file = tmp_path / "outer_block.sv"
@@ -104,7 +101,7 @@ class TestBusDecoderExporter:
         assert "inner" in module_content
         assert "inner_reg" in module_content
 
-    def test_custom_module_name(self, compile_rdl, tmp_path):
+    def test_custom_module_name(self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path) -> None:
         """Test exporting with custom module name."""
         rdl_source = """
         addrmap my_addrmap {
@@ -132,7 +129,7 @@ class TestBusDecoderExporter:
         module_content = module_file.read_text()
         assert "module custom_module" in module_content
 
-    def test_custom_package_name(self, compile_rdl, tmp_path):
+    def test_custom_package_name(self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path) -> None:
         """Test exporting with custom package name."""
         rdl_source = """
         addrmap my_addrmap {
@@ -157,7 +154,7 @@ class TestBusDecoderExporter:
         package_content = package_file.read_text()
         assert "package custom_pkg" in package_content
 
-    def test_multiple_registers(self, compile_rdl, tmp_path):
+    def test_multiple_registers(self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path) -> None:
         """Test exporting multiple registers."""
         rdl_source = """
         addrmap multi_reg {
@@ -198,61 +195,89 @@ class TestBusDecoderExporter:
         assert "reg2" in module_content
         assert "reg3" in module_content
 
-
+    def test_master_address_widths_export(
-class TestAPB4Interface:
+        self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path
-    """Test APB4 CPU interface generation."""
+    ) -> None:
-
+        """Test exporting master address width parameters for child addrmaps."""
-    def test_apb4_port_declaration(self, compile_rdl, tmp_path):
-        """Test that APB4 interface ports are generated."""
         rdl_source = """
-        addrmap apb_test {
+        addrmap child1 {
             reg {
                 field {
                     sw=rw;
                     hw=r;
                 } data[31:0];
-            } my_reg @ 0x0;
+            } reg1 @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="apb_test")
-
-        exporter = BusDecoderExporter()
-        output_dir = str(tmp_path)
-        exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
-
-        module_file = tmp_path / "apb_test.sv"
-        module_content = module_file.read_text()
-
-        # Check for APB4 signals
-        assert "PSEL" in module_content or "psel" in module_content
-        assert "PENABLE" in module_content or "penable" in module_content
-        assert "PWRITE" in module_content or "pwrite" in module_content
-        assert "PADDR" in module_content or "paddr" in module_content
-        assert "PWDATA" in module_content or "pwdata" in module_content
-        assert "PRDATA" in module_content or "prdata" in module_content
-        assert "PREADY" in module_content or "pready" in module_content
-
-    def test_apb4_read_write_logic(self, compile_rdl, tmp_path):
-        """Test that APB4 read/write logic is generated."""
-        rdl_source = """
-        addrmap apb_rw {
             reg {
                 field {
                     sw=rw;
                     hw=r;
                 } data[31:0];
-            } my_reg @ 0x0;
+            } reg2 @ 0x4;
+        };
+        
+        addrmap child2 {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[15:0];
+            } reg2 @ 0x0;
+        };
+        
+        addrmap parent {
+            external child1 c1 @ 0x0000;
+            external child2 c2 @ 0x1000;
         };
         """
-        top = compile_rdl(rdl_source, top="apb_rw")
+        top = compile_rdl(rdl_source, top="parent")
 
         exporter = BusDecoderExporter()
         output_dir = str(tmp_path)
         exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
 
-        module_file = tmp_path / "apb_rw.sv"
+        package_file = tmp_path / "parent_pkg.sv"
-        module_content = module_file.read_text()
+        assert package_file.exists()
 
-        # Basic sanity checks for logic generation
+        package_content = package_file.read_text()
-        assert "always" in module_content or "assign" in module_content
+        assert "package parent_pkg" in package_content
-        assert "my_reg" in module_content
+        # Check for master address width parameters
+        assert "localparam PARENT_C1_ADDR_WIDTH = 3" in package_content
+        assert "localparam PARENT_C2_ADDR_WIDTH = 2" in package_content
+
+    def test_master_address_widths_with_arrays(
+        self, compile_rdl: Callable[..., AddrmapNode], tmp_path: Path
+    ) -> None:
+        """Test exporting master address width parameters for arrayed child addrmaps."""
+        rdl_source = """
+        addrmap child {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } reg1 @ 0x0;
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } reg2 @ 0x4;
+        };
+        
+        addrmap parent {
+            external child children[4] @ 0x0 += 0x100;
+        };
+        """
+        top = compile_rdl(rdl_source, top="parent")
+
+        exporter = BusDecoderExporter()
+        output_dir = str(tmp_path)
+        exporter.export(top, output_dir, cpuif_cls=APB4Cpuif)
+
+        package_file = tmp_path / "parent_pkg.sv"
+        assert package_file.exists()
+
+        package_content = package_file.read_text()
+        assert "package parent_pkg" in package_content
+        # Check for master address width parameter - array should have a single parameter
+        assert "localparam PARENT_CHILDREN_ADDR_WIDTH = 3" in package_content

tests/generator/test_decode_logic_generator.py

@@ -0,0 +1,96 @@
+from collections.abc import Callable
+
+from systemrdl.node import AddrmapNode
+
+from peakrdl_busdecoder.decode_logic_gen import DecodeLogicFlavor, DecodeLogicGenerator
+from peakrdl_busdecoder.design_state import DesignState
+
+
+class TestDecodeLogicGenerator:
+    """Test the DecodeLogicGenerator."""
+
+    def test_decode_logic_read(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
+        """Test decode logic generation for read operations."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {})
+        gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
+
+        # Basic sanity check - it should initialize
+        assert gen is not None
+        assert gen._flavor == DecodeLogicFlavor.READ  # type: ignore
+
+    def test_decode_logic_write(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
+        """Test decode logic generation for write operations."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {})
+        gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.WRITE)
+
+        assert gen is not None
+        assert gen._flavor == DecodeLogicFlavor.WRITE  # type: ignore
+
+    def test_cpuif_addr_predicate(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
+        """Test address predicate generation."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x100;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {})
+        gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
+
+        # Get the register node
+        reg_node = None
+        for child in top.children():
+            if child.inst_name == "my_reg":
+                reg_node = child
+                break
+        assert reg_node is not None
+
+        predicates = gen.cpuif_addr_predicate(reg_node)
+
+        # Should return a list of conditions
+        assert isinstance(predicates, list)
+        assert len(predicates) > 0
+        # Should check address bounds
+        for pred in predicates:
+            assert "cpuif_rd_addr" in pred or ">=" in pred or "<" in pred
+
+    def test_decode_logic_flavor_enum(self) -> None:
+        """Test DecodeLogicFlavor enum values."""
+        assert DecodeLogicFlavor.READ.value == "rd"
+        assert DecodeLogicFlavor.WRITE.value == "wr"
+
+        assert DecodeLogicFlavor.READ.cpuif_address == "cpuif_rd_addr"
+        assert DecodeLogicFlavor.WRITE.cpuif_address == "cpuif_wr_addr"
+
+        assert DecodeLogicFlavor.READ.cpuif_select == "cpuif_rd_sel"
+        assert DecodeLogicFlavor.WRITE.cpuif_select == "cpuif_wr_sel"

tests/generator/test_design_state.py

@@ -0,0 +1,125 @@
+
+from collections.abc import Callable
+
+from systemrdl.node import AddrmapNode
+
+from peakrdl_busdecoder.design_state import DesignState
+
+
+class TestDesignState:
+    """Test the DesignState class."""
+
+    def test_design_state_basic(self, compile_rdl:Callable[..., AddrmapNode])->None:
+        """Test basic DesignState initialization."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {})
+
+        assert ds.top_node == top
+        assert ds.module_name == "test"
+        assert ds.package_name == "test_pkg"
+        assert ds.cpuif_data_width == 32  # Should infer from 32-bit field
+        assert ds.addr_width > 0
+
+    def test_design_state_custom_module_name(self, compile_rdl:Callable[..., AddrmapNode])->None:
+        """Test DesignState with custom module name."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {"module_name": "custom_module"})
+
+        assert ds.module_name == "custom_module"
+        assert ds.package_name == "custom_module_pkg"
+
+    def test_design_state_custom_package_name(self, compile_rdl:Callable[..., AddrmapNode])->None:
+        """Test DesignState with custom package name."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {"package_name": "custom_pkg"})
+
+        assert ds.package_name == "custom_pkg"
+
+    def test_design_state_custom_address_width(self, compile_rdl:Callable[..., AddrmapNode])->None:
+        """Test DesignState with custom address width."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {"address_width": 16})
+
+        assert ds.addr_width == 16
+
+    def test_design_state_unroll_arrays(self, compile_rdl:Callable[..., AddrmapNode])->None:
+        """Test DesignState with cpuif_unroll option."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_regs[4] @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {"cpuif_unroll": True})
+
+        assert ds.cpuif_unroll is True
+
+    def test_design_state_64bit_registers(self, compile_rdl:Callable[..., AddrmapNode])->None:
+        """Test DesignState with wider data width."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                regwidth = 32;
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {})
+
+        # Should infer 32-bit data width from field
+        assert ds.cpuif_data_width == 32

tests/generator/test_questa_compatibility.py

@@ -0,0 +1,131 @@
+"""Test Questa simulator compatibility for instance arrays."""
+
+from collections.abc import Callable
+from pathlib import Path
+from tempfile import TemporaryDirectory
+
+from systemrdl.node import AddrmapNode
+
+from peakrdl_busdecoder import BusDecoderExporter
+from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
+
+
+def test_instance_array_questa_compatibility(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that instance arrays generate Questa-compatible code.
+    
+    This test ensures that:
+    - Struct members for arrays use unpacked array syntax (name[dim])
+    - NOT packed bit-vector syntax ([dim-1:0]name)
+    - Struct is unpacked (not packed)
+    - Array indexing with loop variables works correctly
+    
+    This fixes the error: "Nonconstant index into instance array"
+    """
+    rdl_source = """
+    addrmap test_map {
+        reg {
+            field {
+                sw=rw;
+                hw=r;
+            } data[31:0];
+        } my_reg[4] @ 0x0 += 0x10;
+    };
+    """
+    top = compile_rdl(rdl_source, top="test_map")
+    
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif)
+        
+        # Read the generated module
+        module_file = Path(tmpdir) / "test_map.sv"
+        content = module_file.read_text()
+        
+        # Should use unpacked struct
+        assert "typedef struct {" in content
+        assert "typedef struct packed" not in content
+        
+        # Should use unpacked array syntax for array members
+        assert "logic my_reg[4];" in content
+        
+        # Should NOT use packed bit-vector syntax
+        assert "[3:0]my_reg" not in content
+        
+        # Should have proper array indexing in decode logic
+        assert "cpuif_wr_sel.my_reg[i0] = 1'b1;" in content
+        assert "cpuif_rd_sel.my_reg[i0] = 1'b1;" in content
+        
+        # Should have proper array indexing in fanout/fanin logic
+        assert "cpuif_wr_sel.my_reg[gi0]" in content or "cpuif_rd_sel.my_reg[gi0]" in content
+        assert "cpuif_wr_sel.my_reg[i0]" in content or "cpuif_rd_sel.my_reg[i0]" in content
+
+
+def test_multidimensional_array_questa_compatibility(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that multidimensional instance arrays generate Questa-compatible code."""
+    rdl_source = """
+    addrmap test_map {
+        reg {
+            field {
+                sw=rw;
+                hw=r;
+            } data[31:0];
+        } my_reg[2][3] @ 0x0 += 0x10;
+    };
+    """
+    top = compile_rdl(rdl_source, top="test_map")
+    
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif)
+        
+        # Read the generated module
+        module_file = Path(tmpdir) / "test_map.sv"
+        content = module_file.read_text()
+        
+        # Should use unpacked struct with multidimensional array
+        assert "typedef struct {" in content
+        
+        # Should use unpacked array syntax for multidimensional arrays
+        assert "logic my_reg[2][3];" in content
+        
+        # Should NOT use packed bit-vector syntax
+        assert "[1:0][2:0]my_reg" not in content
+        assert "[5:0]my_reg" not in content
+
+
+def test_nested_instance_array_questa_compatibility(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that nested instance arrays generate Questa-compatible code."""
+    rdl_source = """
+    addrmap inner_map {
+        reg {
+            field {
+                sw=rw;
+                hw=r;
+            } data[31:0];
+        } inner_reg[2] @ 0x0 += 0x10;
+    };
+    
+    addrmap outer_map {
+        inner_map inner[3] @ 0x0 += 0x100;
+    };
+    """
+    top = compile_rdl(rdl_source, top="outer_map")
+    
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif)
+        
+        # Read the generated module
+        module_file = Path(tmpdir) / "outer_map.sv"
+        content = module_file.read_text()
+        
+        # Should use unpacked struct
+        assert "typedef struct {" in content
+        
+        # Inner should be an array
+        # The exact syntax may vary, but it should be unpacked
+        # Look for the pattern of unpacked arrays, not packed bit-vectors
+        assert "inner[3]" in content or "logic inner" in content
+        
+        # Should NOT use packed bit-vector syntax like [2:0]inner
+        assert "[2:0]inner" not in content

tests/generator/test_struct_generator.py

@@ -0,0 +1,105 @@
+from collections.abc import Callable
+
+from systemrdl.node import AddrmapNode
+
+from peakrdl_busdecoder.design_state import DesignState
+from peakrdl_busdecoder.struct_gen import StructGenerator
+
+
+class TestStructGenerator:
+    """Test the StructGenerator."""
+
+    def test_simple_struct_generation(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
+        """Test struct generation for simple register."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_reg @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {})
+        gen = StructGenerator(ds)
+
+        # Should generate struct definition
+        assert gen is not None
+        result = str(gen)
+
+        # Should contain struct declaration
+        assert "struct" in result or "typedef" in result
+
+    def test_nested_struct_generation(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
+        """Test struct generation for nested addrmaps."""
+        rdl_source = """
+        addrmap inner {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } inner_reg @ 0x0;
+        };
+        
+        addrmap outer {
+            inner my_inner @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="outer")
+
+        ds = DesignState(top, {})
+        gen = StructGenerator(ds)
+
+        # Walk the tree to generate structs
+        from systemrdl.walker import RDLWalker
+
+        walker = RDLWalker()
+        walker.walk(top, gen, skip_top=True)
+
+        result = str(gen)
+
+        # Should contain struct declaration
+        assert "struct" in result or "typedef" in result
+        # The struct should reference the inner component
+        assert "my_inner" in result
+
+    def test_array_struct_generation(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
+        """Test struct generation for register arrays."""
+        rdl_source = """
+        addrmap test {
+            reg {
+                field {
+                    sw=rw;
+                    hw=r;
+                } data[31:0];
+            } my_regs[4] @ 0x0;
+        };
+        """
+        top = compile_rdl(rdl_source, top="test")
+
+        ds = DesignState(top, {})
+        gen = StructGenerator(ds)
+
+        # Walk the tree to generate structs
+        from systemrdl.walker import RDLWalker
+
+        walker = RDLWalker()
+        walker.walk(top, gen, skip_top=True)
+
+        result = str(gen)
+
+        # Should contain array notation
+        assert "[" in result and "]" in result
+        # Should reference the register
+        assert "my_regs" in result
+        # Should use unpacked array syntax (name[size]), not packed bit-vector ([size:0]name)
+        assert "my_regs[4]" in result
+        # Should NOT use packed bit-vector syntax
+        assert "[3:0]my_regs" not in result
+        # Should be unpacked struct, not packed
+        assert "typedef struct {" in result
+        assert "typedef struct packed" not in result

tests/pytest.ini

@@ -1,3 +0,0 @@
-[pytest]
-testpaths = unit
-python_files = test_*.py testcase.py

tests/unit/__init__.py

@@ -1 +0,0 @@
-"""Unit test package for PeakRDL BusDecoder."""

tests/unit/conftest.py

@@ -1,56 +1,75 @@
 """Pytest fixtures for unit tests."""
 
-from __future__ import annotations
+
 
 from pathlib import Path
 from tempfile import NamedTemporaryFile
 from typing import Iterable, Mapping, Optional
+from collections.abc import Callable
 
 import pytest
-from systemrdl import RDLCompileError, RDLCompiler
+from systemrdl.node import AddrmapNode
 
 
 @pytest.fixture
-def compile_rdl(tmp_path: Path):
+def external_nested_rdl(compile_rdl: Callable[..., AddrmapNode]) -> AddrmapNode:
-    """Compile inline SystemRDL source and return the elaborated root node.
+    """Create an RDL design with external nested addressable components.
 
-    Parameters
+    This tests the scenario where an addrmap contains external children
-    ----------
+    that themselves have external addressable children.
-    tmp_path:
+    The decoder should only generate select signals for the top-level
-        Temporary directory provided by pytest.
+    external children, not their internal structure.
     """
+    rdl_source = """
+    mem queue_t {
+        name = "Queue";
+        mementries = 1024;
+        memwidth = 64;
+    };
 
-    def _compile(
+    addrmap port_t {
-        source: str,
+        name = "Port";
-        *,
+        desc = "";
-        top: Optional[str] = None,
-        defines: Optional[Mapping[str, object]] = None,
-        include_paths: Optional[Iterable[Path | str]] = None,
-    ):
-        compiler = RDLCompiler()
 
-        for key, value in (defines or {}).items():
+        external queue_t common[3] @ 0x0 += 0x2000;
-            compiler.define(key, value)
+        external queue_t response  @ 0x6000;
+    };
 
-        for include_path in include_paths or ():
+    addrmap buffer_t {
-            compiler.add_include_path(str(include_path))
+        name = "Buffer";
+        desc = "";
 
-        # Use delete=False to keep the file around after closing
+        port_t multicast      @ 0x0;
-        with NamedTemporaryFile("w", suffix=".rdl", dir=tmp_path, delete=False) as tmp_file:
+        port_t port      [16] @ 0x8000 += 0x8000;
-            tmp_file.write(source)
+    };
-            tmp_file.flush()
+    """
+    return compile_rdl(rdl_source, top="buffer_t")
 
-            try:
-                compiler.compile_file(tmp_file.name)
-                if top is not None:
-                    root = compiler.elaborate(top)
-                    return root.top
-                root = compiler.elaborate()
-                return root.top
-            except RDLCompileError:
-                # Print error messages if available
-                if hasattr(compiler, "print_messages"):
-                    compiler.print_messages()
-                raise
 
-    return _compile
+@pytest.fixture
+def nested_addrmap_rdl(compile_rdl: Callable[..., AddrmapNode]) -> AddrmapNode:
+    """Create an RDL design with nested non-external addrmaps for testing depth control."""
+    rdl_source = """
+    addrmap level2 {
+        reg {
+            field { sw=rw; hw=r; } data2[31:0];
+        } reg2 @ 0x0;
+        
+        reg {
+            field { sw=rw; hw=r; } data2b[31:0];
+        } reg2b @ 0x4;
+    };
+
+    addrmap level1 {
+        reg {
+            field { sw=rw; hw=r; } data1[31:0];
+        } reg1 @ 0x0;
+        
+        level2 inner2 @ 0x10;
+    };
+
+    addrmap level0 {
+        level1 inner1 @ 0x0;
+    };
+    """
+    return compile_rdl(rdl_source, top="level0")

tests/unit/test_body.py

@@ -1,285 +0,0 @@
-"""Tests for body classes used in code generation."""
-
-from __future__ import annotations
-
-import pytest
-
-from peakrdl_busdecoder.body import (
-    Body,
-    CombinationalBody,
-    ForLoopBody,
-    IfBody,
-    StructBody,
-)
-
-
-class TestBody:
-    """Test the base Body class."""
-
-    def test_empty_body(self):
-        """Test empty body returns empty string."""
-        body = Body()
-        assert str(body) == ""
-        assert not body  # Should be falsy when empty
-
-    def test_add_single_line(self):
-        """Test adding a single line to body."""
-        body = Body()
-        body += "line1"
-        assert str(body) == "line1"
-        assert body  # Should be truthy when not empty
-
-    def test_add_multiple_lines(self):
-        """Test adding multiple lines to body."""
-        body = Body()
-        body += "line1"
-        body += "line2"
-        body += "line3"
-        expected = "line1\nline2\nline3"
-        assert str(body) == expected
-
-    def test_add_returns_self(self):
-        """Test that add operation returns self for chaining."""
-        body = Body()
-        body += "line1"
-        body += "line2"
-        # Chaining works because += returns self
-        assert len(body.lines) == 2
-
-    def test_add_nested_body(self):
-        """Test adding another body as a line."""
-        outer = Body()
-        inner = Body()
-        inner += "inner1"
-        inner += "inner2"
-        outer += "outer1"
-        outer += inner
-        outer += "outer2"
-        expected = "outer1\ninner1\ninner2\nouter2"
-        assert str(outer) == expected
-
-
-class TestForLoopBody:
-    """Test the ForLoopBody class."""
-
-    def test_genvar_for_loop(self):
-        """Test genvar-style for loop."""
-        body = ForLoopBody("genvar", "i", 4)
-        body += "statement1;"
-        body += "statement2;"
-
-        result = str(body)
-        assert "for (genvar i = 0; i < 4; i++)" in result
-        assert "statement1;" in result
-        assert "statement2;" in result
-        assert "end" in result
-
-    def test_int_for_loop(self):
-        """Test int-style for loop."""
-        body = ForLoopBody("int", "j", 8)
-        body += "assignment = value;"
-
-        result = str(body)
-        assert "for (int j = 0; j < 8; j++)" in result
-        assert "assignment = value;" in result
-        assert "end" in result
-
-    def test_empty_for_loop(self):
-        """Test empty for loop."""
-        body = ForLoopBody("genvar", "k", 2)
-        result = str(body)
-        # Empty for loop should still have structure
-        assert "for (genvar k = 0; k < 2; k++)" in result
-
-    def test_nested_for_loops(self):
-        """Test nested for loops."""
-        outer = ForLoopBody("genvar", "i", 3)
-        inner = ForLoopBody("genvar", "j", 2)
-        inner += "nested_statement;"
-        outer += inner
-
-        result = str(outer)
-        assert "for (genvar i = 0; i < 3; i++)" in result
-        assert "for (genvar j = 0; j < 2; j++)" in result
-        assert "nested_statement;" in result
-
-
-class TestIfBody:
-    """Test the IfBody class."""
-
-    def test_simple_if(self):
-        """Test simple if statement."""
-        body = IfBody()
-        with body.cm("condition1") as b:
-            b += "statement1;"
-
-        result = str(body)
-        assert "if (condition1)" in result
-        assert "statement1;" in result
-        assert "end" in result
-
-    def test_if_else(self):
-        """Test if-else statement."""
-        body = IfBody()
-        with body.cm("condition1") as b:
-            b += "if_statement;"
-        with body.cm(None) as b:  # None for else
-            b += "else_statement;"
-
-        result = str(body)
-        assert "if (condition1)" in result
-        assert "if_statement;" in result
-        assert "else" in result
-        assert "else_statement;" in result
-
-    def test_if_elif_else(self):
-        """Test if-elif-else chain."""
-        body = IfBody()
-        with body.cm("condition1") as b:
-            b += "statement1;"
-        with body.cm("condition2") as b:
-            b += "statement2;"
-        with body.cm(None) as b:  # None for else
-            b += "statement3;"
-
-        result = str(body)
-        assert "if (condition1)" in result
-        assert "statement1;" in result
-        assert "else if (condition2)" in result
-        assert "statement2;" in result
-        assert "else" in result
-        assert "statement3;" in result
-
-    def test_multiple_elif(self):
-        """Test multiple elif statements."""
-        body = IfBody()
-        with body.cm("cond1") as b:
-            b += "stmt1;"
-        with body.cm("cond2") as b:
-            b += "stmt2;"
-        with body.cm("cond3") as b:
-            b += "stmt3;"
-
-        result = str(body)
-        assert "if (cond1)" in result
-        assert "else if (cond2)" in result
-        assert "else if (cond3)" in result
-
-    def test_empty_if_branches(self):
-        """Test if statement with empty branches."""
-        body = IfBody()
-        with body.cm("condition"):
-            pass
-
-        result = str(body)
-        assert "if (condition)" in result
-
-    def test_nested_if(self):
-        """Test nested if statements."""
-        outer = IfBody()
-        with outer.cm("outer_cond") as outer_body:
-            inner = IfBody()
-            with inner.cm("inner_cond") as inner_body:
-                inner_body += "nested_statement;"
-            outer_body += inner
-
-        result = str(outer)
-        assert "if (outer_cond)" in result
-        assert "if (inner_cond)" in result
-        assert "nested_statement;" in result
-
-
-class TestCombinationalBody:
-    """Test the CombinationalBody class."""
-
-    def test_simple_combinational_block(self):
-        """Test simple combinational block."""
-        body = CombinationalBody()
-        body += "assign1 = value1;"
-        body += "assign2 = value2;"
-
-        result = str(body)
-        assert "always_comb" in result
-        assert "begin" in result
-        assert "assign1 = value1;" in result
-        assert "assign2 = value2;" in result
-        assert "end" in result
-
-    def test_empty_combinational_block(self):
-        """Test empty combinational block."""
-        body = CombinationalBody()
-        result = str(body)
-        assert "always_comb" in result
-        assert "begin" in result
-        assert "end" in result
-
-    def test_combinational_with_if_statement(self):
-        """Test combinational block with if statement."""
-        cb = CombinationalBody()
-        ifb = IfBody()
-        with ifb.cm("condition") as b:
-            b += "assignment = value;"
-        cb += ifb
-
-        result = str(cb)
-        assert "always_comb" in result
-        assert "if (condition)" in result
-        assert "assignment = value;" in result
-
-
-class TestStructBody:
-    """Test the StructBody class."""
-
-    def test_simple_struct(self):
-        """Test simple struct definition."""
-        body = StructBody("my_struct_t", packed=True, typedef=True)
-        body += "logic [7:0] field1;"
-        body += "logic field2;"
-
-        result = str(body)
-        assert "typedef struct packed" in result
-        assert "my_struct_t" in result
-        assert "logic [7:0] field1;" in result
-        assert "logic field2;" in result
-
-    def test_unpacked_struct(self):
-        """Test unpacked struct definition."""
-        body = StructBody("unpacked_t", packed=False, typedef=True)
-        body += "int field1;"
-
-        result = str(body)
-        assert "typedef struct" in result
-        assert "packed" not in result or "typedef struct {" in result
-        assert "unpacked_t" in result
-
-    def test_struct_without_typedef(self):
-        """Test struct without typedef."""
-        body = StructBody("my_struct", packed=True, typedef=False)
-        body += "logic field;"
-
-        result = str(body)
-        # When typedef=False, packed is not used
-        assert "struct {" in result
-        assert "typedef" not in result
-        assert "my_struct" in result
-
-    def test_empty_struct(self):
-        """Test empty struct."""
-        body = StructBody("empty_t", packed=True, typedef=True)
-        result = str(body)
-        assert "typedef struct packed" in result
-        assert "empty_t" in result
-
-    def test_nested_struct(self):
-        """Test struct with nested struct."""
-        outer = StructBody("outer_t", packed=True, typedef=True)
-        inner = StructBody("inner_t", packed=True, typedef=True)
-        inner += "logic field1;"
-        outer += "logic field2;"
-        outer += str(inner)  # Include inner struct as a string
-
-        result = str(outer)
-        assert "outer_t" in result
-        assert "field2;" in result
-        # Inner struct should appear in the string
-        assert "inner_t" in result

tests/unit/test_external_nested.py

@@ -0,0 +1,140 @@
+"""Test handling of external nested addressable components."""
+
+from collections.abc import Callable
+from pathlib import Path
+from tempfile import TemporaryDirectory
+
+from systemrdl.node import AddrmapNode
+
+from peakrdl_busdecoder import BusDecoderExporter
+from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
+
+
+def test_external_nested_components_generate_correct_decoder(external_nested_rdl: AddrmapNode) -> None:
+    """Test that external nested components generate correct decoder logic.
+    
+    The decoder should:
+    - Generate select signals for multicast and port[16]
+    - NOT generate select signals for multicast.common[] or multicast.response
+    - NOT generate invalid paths like multicast.common[i0]
+    """
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(
+            external_nested_rdl,
+            tmpdir,
+            cpuif_cls=APB4Cpuif,
+        )
+        
+        # Read the generated module
+        module_file = Path(tmpdir) / "buffer_t.sv"
+        content = module_file.read_text()
+        
+        # Should have correct select signals
+        assert "cpuif_wr_sel.multicast = 1'b1;" in content
+        assert "cpuif_wr_sel.port[i0] = 1'b1;" in content
+        
+        # Should NOT have invalid nested paths
+        assert "cpuif_wr_sel.multicast.common" not in content
+        assert "cpuif_wr_sel.multicast.response" not in content
+        assert "cpuif_rd_sel.multicast.common" not in content
+        assert "cpuif_rd_sel.multicast.response" not in content
+        
+        # Verify struct is flat (no nested structs for external children)
+        assert "typedef struct" in content
+        assert "logic multicast;" in content
+        assert "logic port[16];" in content
+
+
+def test_external_nested_components_generate_correct_interfaces(external_nested_rdl: AddrmapNode) -> None:
+    """Test that external nested components generate correct interface ports.
+    
+    The module should have:
+    - One master interface for multicast
+    - Array of 16 master interfaces for port[]
+    - NO interfaces for internal components like common[] or response
+    """
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(
+            external_nested_rdl,
+            tmpdir,
+            cpuif_cls=APB4Cpuif,
+        )
+        
+        # Read the generated module
+        module_file = Path(tmpdir) / "buffer_t.sv"
+        content = module_file.read_text()
+        
+        # Should have master interfaces for top-level external children
+        assert "m_apb_multicast" in content
+        assert "m_apb_port [16]" in content or "m_apb_port[16]" in content
+        
+        # Should NOT have interfaces for nested external children
+        assert "m_apb_multicast_common" not in content
+        assert "m_apb_multicast_response" not in content
+        assert "m_apb_common" not in content
+        assert "m_apb_response" not in content
+
+
+def test_non_external_nested_components_are_descended(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that non-external nested components are still descended into.
+    
+    This is a regression test to ensure we didn't break normal nested
+    component handling.
+    """
+    rdl_source = """
+    addrmap inner_block {
+        reg {
+            field {
+                sw=rw;
+                hw=r;
+            } data[31:0];
+        } inner_reg @ 0x0;
+    };
+    
+    addrmap outer_block {
+        inner_block inner @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="outer_block")
+    
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        # Use depth=0 to descend all the way down to registers
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=0)
+        
+        # Read the generated module
+        module_file = Path(tmpdir) / "outer_block.sv"
+        content = module_file.read_text()
+        
+        # Should descend into inner and reference inner_reg
+        assert "inner" in content
+        assert "inner_reg" in content
+
+
+def test_max_decode_depth_parameter_exists(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that max_decode_depth parameter can be set."""
+    rdl_source = """
+    addrmap simple {
+        reg {
+            field { sw=rw; hw=r; } data[31:0];
+        } my_reg @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="simple")
+    
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        # Should not raise an exception
+        exporter.export(
+            top,
+            tmpdir,
+            cpuif_cls=APB4Cpuif,
+            max_decode_depth=2,
+        )
+        
+        # Verify output was generated
+        module_file = Path(tmpdir) / "simple.sv"
+        assert module_file.exists()
+

tests/unit/test_generators.py

@@ -1,312 +0,0 @@
-"""Tests for code generation classes."""
-
-from __future__ import annotations
-
-import pytest
-
-from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
-from peakrdl_busdecoder.decode_logic_gen import DecodeLogicFlavor, DecodeLogicGenerator
-from peakrdl_busdecoder.design_state import DesignState
-from peakrdl_busdecoder.exporter import BusDecoderExporter
-from peakrdl_busdecoder.struct_gen import StructGenerator
-
-
-class TestDecodeLogicGenerator:
-    """Test the DecodeLogicGenerator."""
-
-    def test_decode_logic_read(self, compile_rdl):
-        """Test decode logic generation for read operations."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {})
-        gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
-
-        # Basic sanity check - it should initialize
-        assert gen is not None
-        assert gen._flavor == DecodeLogicFlavor.READ
-
-    def test_decode_logic_write(self, compile_rdl):
-        """Test decode logic generation for write operations."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {})
-        gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.WRITE)
-
-        assert gen is not None
-        assert gen._flavor == DecodeLogicFlavor.WRITE
-
-    def test_cpuif_addr_predicate(self, compile_rdl):
-        """Test address predicate generation."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x100;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {})
-        gen = DecodeLogicGenerator(ds, DecodeLogicFlavor.READ)
-
-        # Get the register node
-        reg_node = None
-        for child in top.children():
-            if child.inst_name == "my_reg":
-                reg_node = child
-                break
-        assert reg_node is not None
-
-        predicates = gen.cpuif_addr_predicate(reg_node)
-
-        # Should return a list of conditions
-        assert isinstance(predicates, list)
-        assert len(predicates) > 0
-        # Should check address bounds
-        for pred in predicates:
-            assert "cpuif_rd_addr" in pred or ">=" in pred or "<" in pred
-
-    def test_decode_logic_flavor_enum(self):
-        """Test DecodeLogicFlavor enum values."""
-        assert DecodeLogicFlavor.READ.value == "rd"
-        assert DecodeLogicFlavor.WRITE.value == "wr"
-
-        assert DecodeLogicFlavor.READ.cpuif_address == "cpuif_rd_addr"
-        assert DecodeLogicFlavor.WRITE.cpuif_address == "cpuif_wr_addr"
-
-        assert DecodeLogicFlavor.READ.cpuif_select == "cpuif_rd_sel"
-        assert DecodeLogicFlavor.WRITE.cpuif_select == "cpuif_wr_sel"
-
-
-class TestStructGenerator:
-    """Test the StructGenerator."""
-
-    def test_simple_struct_generation(self, compile_rdl):
-        """Test struct generation for simple register."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {})
-        gen = StructGenerator(ds)
-
-        # Should generate struct definition
-        assert gen is not None
-        result = str(gen)
-
-        # Should contain struct declaration
-        assert "struct" in result or "typedef" in result
-
-    def test_nested_struct_generation(self, compile_rdl):
-        """Test struct generation for nested addrmaps."""
-        rdl_source = """
-        addrmap inner {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } inner_reg @ 0x0;
-        };
-        
-        addrmap outer {
-            inner my_inner @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="outer")
-
-        ds = DesignState(top, {})
-        gen = StructGenerator(ds)
-
-        # Walk the tree to generate structs
-        from systemrdl.walker import RDLWalker
-
-        walker = RDLWalker()
-        walker.walk(top, gen, skip_top=True)
-
-        result = str(gen)
-
-        # Should contain struct declaration
-        assert "struct" in result or "typedef" in result
-        # The struct should reference the inner component
-        assert "my_inner" in result
-
-    def test_array_struct_generation(self, compile_rdl):
-        """Test struct generation for register arrays."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_regs[4] @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {})
-        gen = StructGenerator(ds)
-
-        # Walk the tree to generate structs
-        from systemrdl.walker import RDLWalker
-
-        walker = RDLWalker()
-        walker.walk(top, gen, skip_top=True)
-
-        result = str(gen)
-
-        # Should contain array notation
-        assert "[" in result and "]" in result
-        # Should reference the register
-        assert "my_regs" in result
-
-
-class TestDesignState:
-    """Test the DesignState class."""
-
-    def test_design_state_basic(self, compile_rdl):
-        """Test basic DesignState initialization."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {})
-
-        assert ds.top_node == top
-        assert ds.module_name == "test"
-        assert ds.package_name == "test_pkg"
-        assert ds.cpuif_data_width == 32  # Should infer from 32-bit field
-        assert ds.addr_width > 0
-
-    def test_design_state_custom_module_name(self, compile_rdl):
-        """Test DesignState with custom module name."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {"module_name": "custom_module"})
-
-        assert ds.module_name == "custom_module"
-        assert ds.package_name == "custom_module_pkg"
-
-    def test_design_state_custom_package_name(self, compile_rdl):
-        """Test DesignState with custom package name."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {"package_name": "custom_pkg"})
-
-        assert ds.package_name == "custom_pkg"
-
-    def test_design_state_custom_address_width(self, compile_rdl):
-        """Test DesignState with custom address width."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {"address_width": 16})
-
-        assert ds.addr_width == 16
-
-    def test_design_state_unroll_arrays(self, compile_rdl):
-        """Test DesignState with cpuif_unroll option."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_regs[4] @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {"cpuif_unroll": True})
-
-        assert ds.cpuif_unroll is True
-
-    def test_design_state_64bit_registers(self, compile_rdl):
-        """Test DesignState with wider data width."""
-        rdl_source = """
-        addrmap test {
-            reg {
-                regwidth = 32;
-                field {
-                    sw=rw;
-                    hw=r;
-                } data[31:0];
-            } my_reg @ 0x0;
-        };
-        """
-        top = compile_rdl(rdl_source, top="test")
-
-        ds = DesignState(top, {})
-
-        # Should infer 32-bit data width from field
-        assert ds.cpuif_data_width == 32

tests/unit/test_max_decode_depth.py

@@ -0,0 +1,256 @@
+"""Test max_decode_depth parameter behavior."""
+
+from collections.abc import Callable
+from pathlib import Path
+from tempfile import TemporaryDirectory
+
+from systemrdl.node import AddrmapNode
+
+from peakrdl_busdecoder import BusDecoderExporter
+from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
+
+
+def test_depth_1_generates_top_level_interface_only(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that depth=1 generates interface only for top-level children."""
+    rdl_source = """
+    addrmap level1 {
+        reg {
+            field { sw=rw; hw=r; } data1[31:0];
+        } reg1 @ 0x0;
+    };
+
+    addrmap level0 {
+        level1 inner1 @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="level0")
+
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=1)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        # Should have interface for inner1 only
+        assert "m_apb_inner1" in content
+        # Should NOT have interface for reg1
+        assert "m_apb_reg1" not in content
+        
+        # Struct should have inner1 but not nested structure
+        assert "logic inner1;" in content
+
+
+def test_depth_2_generates_second_level_interfaces(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that depth=2 generates interfaces for second-level children."""
+    rdl_source = """
+    addrmap level2 {
+        reg {
+            field { sw=rw; hw=r; } data2[31:0];
+        } reg2 @ 0x0;
+    };
+
+    addrmap level1 {
+        reg {
+            field { sw=rw; hw=r; } data1[31:0];
+        } reg1 @ 0x0;
+        
+        level2 inner2 @ 0x10;
+    };
+
+    addrmap level0 {
+        level1 inner1 @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="level0")
+
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=2)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        # Should have interfaces for reg1 and inner2
+        assert "m_apb_reg1" in content
+        assert "m_apb_inner2" in content
+        # Should NOT have interface for inner1 or reg2
+        assert "m_apb_inner1" not in content
+        assert "m_apb_reg2" not in content
+        
+        # Struct should be hierarchical with inner1.reg1 and inner1.inner2
+        assert "cpuif_sel_inner1_t" in content
+        assert "logic reg1;" in content
+        assert "logic inner2;" in content
+
+
+def test_depth_0_decodes_all_levels(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that depth=0 decodes all the way down to registers."""
+    rdl_source = """
+    addrmap level2 {
+        reg {
+            field { sw=rw; hw=r; } data2[31:0];
+        } reg2 @ 0x0;
+        
+        reg {
+            field { sw=rw; hw=r; } data2b[31:0];
+        } reg2b @ 0x4;
+    };
+
+    addrmap level1 {
+        reg {
+            field { sw=rw; hw=r; } data1[31:0];
+        } reg1 @ 0x0;
+        
+        level2 inner2 @ 0x10;
+    };
+
+    addrmap level0 {
+        level1 inner1 @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="level0")
+
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=0)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        # Should have interfaces for all leaf registers
+        assert "m_apb_reg1" in content
+        assert "m_apb_reg2" in content
+        assert "m_apb_reg2b" in content
+        # Should NOT have interfaces for addrmaps
+        assert "m_apb_inner1" not in content
+        assert "m_apb_inner2" not in content
+        
+        # Struct should be fully hierarchical
+        assert "cpuif_sel_inner1_t" in content
+        assert "cpuif_sel_inner2_t" in content
+
+
+def test_depth_affects_decode_logic(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that decode logic changes based on max_decode_depth."""
+    rdl_source = """
+    addrmap level1 {
+        reg {
+            field { sw=rw; hw=r; } data1[31:0];
+        } reg1 @ 0x0;
+    };
+
+    addrmap level0 {
+        level1 inner1 @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="level0")
+
+    # Test depth=1: should set cpuif_wr_sel.inner1
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=1)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        assert "cpuif_wr_sel.inner1 = 1'b1;" in content
+        assert "cpuif_wr_sel.inner1.reg1" not in content
+
+    # Test depth=2: should set cpuif_wr_sel.inner1.reg1
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=2)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        assert "cpuif_wr_sel.inner1.reg1 = 1'b1;" in content
+        assert "cpuif_wr_sel.inner1 = 1'b1;" not in content
+
+
+def test_depth_affects_fanout_fanin(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test that fanout/fanin logic changes based on max_decode_depth."""
+    rdl_source = """
+    addrmap level1 {
+        reg {
+            field { sw=rw; hw=r; } data1[31:0];
+        } reg1 @ 0x0;
+    };
+
+    addrmap level0 {
+        level1 inner1 @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="level0")
+
+    # Test depth=1: should have fanout for inner1
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=1)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        assert "m_apb_inner1.PSEL" in content
+        assert "m_apb_reg1.PSEL" not in content
+
+    # Test depth=2: should have fanout for reg1
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=2)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        assert "m_apb_reg1.PSEL" in content
+        assert "m_apb_inner1.PSEL" not in content
+
+
+def test_depth_3_with_deep_hierarchy(compile_rdl: Callable[..., AddrmapNode]) -> None:
+    """Test depth=3 with a 4-level deep hierarchy."""
+    rdl_source = """
+    addrmap level3 {
+        reg {
+            field { sw=rw; hw=r; } data3[31:0];
+        } reg3 @ 0x0;
+    };
+
+    addrmap level2 {
+        reg {
+            field { sw=rw; hw=r; } data2[31:0];
+        } reg2 @ 0x0;
+        
+        level3 inner3 @ 0x10;
+    };
+
+    addrmap level1 {
+        reg {
+            field { sw=rw; hw=r; } data1[31:0];
+        } reg1 @ 0x0;
+        
+        level2 inner2 @ 0x10;
+    };
+
+    addrmap level0 {
+        level1 inner1 @ 0x0;
+    };
+    """
+    top = compile_rdl(rdl_source, top="level0")
+
+    with TemporaryDirectory() as tmpdir:
+        exporter = BusDecoderExporter()
+        exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif, max_decode_depth=3)
+
+        module_file = Path(tmpdir) / "level0.sv"
+        content = module_file.read_text()
+
+        # Should have interfaces at depth 3: reg2, inner3
+        # (reg1 is at depth 2, not 3)
+        assert "m_apb_reg2" in content
+        assert "m_apb_inner3" in content
+        # Should NOT have interfaces at other depths
+        assert "m_apb_inner1" not in content
+        assert "m_apb_inner2" not in content
+        assert "m_apb_reg1" not in content
+        assert "m_apb_reg3" not in content

tests/unroll/conftest.py

@@ -0,0 +1,40 @@
+from collections.abc import Callable
+
+import pytest
+from systemrdl.node import AddrmapNode
+
+
+@pytest.fixture
+def sample_rdl(compile_rdl: Callable[..., AddrmapNode]) -> AddrmapNode:
+    """Create a simple RDL design with an array."""
+    rdl_source = """
+    addrmap top {
+        reg my_reg {
+            field {
+                sw=rw;
+                hw=r;
+            } data[31:0];
+        };
+        
+        my_reg regs[4] @ 0x0 += 0x4;
+    };
+    """
+    return compile_rdl(rdl_source)
+
+
+@pytest.fixture
+def multidim_array_rdl(compile_rdl: Callable[..., AddrmapNode]) -> AddrmapNode:
+    """Create an RDL design with a multi-dimensional array."""
+    rdl_source = """
+    addrmap top {
+        reg my_reg {
+            field {
+                sw=rw;
+                hw=r;
+            } data[31:0];
+        };
+        
+        my_reg matrix[2][3] @ 0x0 += 0x4;
+    };
+    """
+    return compile_rdl(rdl_source)

tests/unroll/test_unroll.py

@@ -1,34 +1,14 @@
-"""Test the --unroll CLI argument functionality."""
-
 from pathlib import Path
 from tempfile import TemporaryDirectory
 
-import pytest
+from systemrdl.node import AddrmapNode
 
 from peakrdl_busdecoder import BusDecoderExporter
 from peakrdl_busdecoder.cpuif.apb3 import APB3Cpuif
 from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
 
 
-@pytest.fixture
+def test_unroll_disabled_creates_array_interface(sample_rdl: AddrmapNode) -> None:
-def sample_rdl(compile_rdl):
-    """Create a simple RDL design with an array."""
-    rdl_source = """
-    addrmap top {
-        reg my_reg {
-            field {
-                sw=rw;
-                hw=r;
-            } data[31:0];
-        };
-        
-        my_reg regs[4] @ 0x0 += 0x4;
-    };
-    """
-    return compile_rdl(rdl_source)
-
-
-def test_unroll_disabled_creates_array_interface(sample_rdl):
     """Test that with unroll=False, array nodes are kept as arrays."""
     with TemporaryDirectory() as tmpdir:
         exporter = BusDecoderExporter()
@@ -38,17 +18,17 @@ def test_unroll_disabled_creates_array_interface(sample_rdl):
             cpuif_cls=APB4Cpuif,
             cpuif_unroll=False,
         )
-        
+
         # Read the generated module
         module_file = Path(tmpdir) / "top.sv"
         content = module_file.read_text()
-        
+
         # Should have a single array interface with [4] dimension
         assert "m_apb_regs [4]" in content
-        
+
         # Should have a parameter for array size
         assert "N_REGSS = 4" in content
-        
+
         # Should NOT have individual indexed interfaces
         assert "m_apb_regs_0" not in content
         assert "m_apb_regs_1" not in content
@@ -56,7 +36,7 @@ def test_unroll_disabled_creates_array_interface(sample_rdl):
         assert "m_apb_regs_3" not in content
 
 
-def test_unroll_enabled_creates_individual_interfaces(sample_rdl):
+def test_unroll_enabled_creates_individual_interfaces(sample_rdl: AddrmapNode) -> None:
     """Test that with unroll=True, array elements are unrolled into separate instances."""
     with TemporaryDirectory() as tmpdir:
         exporter = BusDecoderExporter()
@@ -66,31 +46,31 @@ def test_unroll_enabled_creates_individual_interfaces(sample_rdl):
             cpuif_cls=APB4Cpuif,
             cpuif_unroll=True,
         )
-        
+
         # Read the generated module
         module_file = Path(tmpdir) / "top.sv"
         content = module_file.read_text()
-        
+
         # Should have individual interfaces without array dimensions
         assert "m_apb_regs_0," in content or "m_apb_regs_0\n" in content
         assert "m_apb_regs_1," in content or "m_apb_regs_1\n" in content
         assert "m_apb_regs_2," in content or "m_apb_regs_2\n" in content
         assert "m_apb_regs_3" in content
-        
+
         # Should NOT have array interface
         assert "m_apb_regs [4]" not in content
-        
+
         # Should NOT have individual interfaces with array dimensions (the bug we're fixing)
         assert "m_apb_regs_0 [4]" not in content
         assert "m_apb_regs_1 [4]" not in content
         assert "m_apb_regs_2 [4]" not in content
         assert "m_apb_regs_3 [4]" not in content
-        
+
         # Should NOT have array size parameter when unrolled
         assert "N_REGSS" not in content
 
 
-def test_unroll_with_apb3(sample_rdl):
+def test_unroll_with_apb3(sample_rdl: AddrmapNode) -> None:
     """Test that unroll works correctly with APB3 interface."""
     with TemporaryDirectory() as tmpdir:
         exporter = BusDecoderExporter()
@@ -100,40 +80,22 @@ def test_unroll_with_apb3(sample_rdl):
             cpuif_cls=APB3Cpuif,
             cpuif_unroll=True,
         )
-        
+
         # Read the generated module
         module_file = Path(tmpdir) / "top.sv"
         content = module_file.read_text()
-        
+
         # Should have individual APB3 interfaces
         assert "m_apb_regs_0," in content or "m_apb_regs_0\n" in content
         assert "m_apb_regs_1," in content or "m_apb_regs_1\n" in content
         assert "m_apb_regs_2," in content or "m_apb_regs_2\n" in content
         assert "m_apb_regs_3" in content
-        
+
         # Should NOT have array dimensions on unrolled interfaces
         assert "m_apb_regs_0 [4]" not in content
 
 
-@pytest.fixture
+def test_unroll_multidimensional_array(multidim_array_rdl: AddrmapNode) -> None:
-def multidim_array_rdl(compile_rdl):
-    """Create an RDL design with a multi-dimensional array."""
-    rdl_source = """
-    addrmap top {
-        reg my_reg {
-            field {
-                sw=rw;
-                hw=r;
-            } data[31:0];
-        };
-        
-        my_reg matrix[2][3] @ 0x0 += 0x4;
-    };
-    """
-    return compile_rdl(rdl_source)
-
-
-def test_unroll_multidimensional_array(multidim_array_rdl):
     """Test that unroll works correctly with multi-dimensional arrays."""
     with TemporaryDirectory() as tmpdir:
         exporter = BusDecoderExporter()
@@ -143,11 +105,11 @@ def test_unroll_multidimensional_array(multidim_array_rdl):
             cpuif_cls=APB4Cpuif,
             cpuif_unroll=True,
         )
-        
+
         # Read the generated module
         module_file = Path(tmpdir) / "top.sv"
         content = module_file.read_text()
-        
+
         # Should have individual interfaces for each element in the 2x3 array
         # Format should be m_apb_matrix_0_0, m_apb_matrix_0_1, ..., m_apb_matrix_1_2
         assert "m_apb_matrix_0_0" in content
@@ -156,7 +118,7 @@ def test_unroll_multidimensional_array(multidim_array_rdl):
         assert "m_apb_matrix_1_0" in content
         assert "m_apb_matrix_1_1" in content
         assert "m_apb_matrix_1_2" in content
-        
+
         # Should NOT have array dimensions on any of the unrolled interfaces
         for i in range(2):
             for j in range(3):

tests/utils/test_get_indexed_path.py

@@ -1,96 +1,14 @@
-"""Tests for utility functions."""
+from collections.abc import Callable
 
-from __future__ import annotations
-
-import pytest
-from systemrdl import RDLCompiler
 from systemrdl.node import AddrmapNode
 
-from peakrdl_busdecoder.utils import clog2, get_indexed_path, is_pow2, roundup_pow2
+from peakrdl_busdecoder.utils import get_indexed_path
-
-
-class TestMathUtils:
-    """Test mathematical utility functions."""
-
-    def test_clog2_basic(self):
-        """Test clog2 function with basic values."""
-        assert clog2(1) == 0
-        assert clog2(2) == 1
-        assert clog2(3) == 2
-        assert clog2(4) == 2
-        assert clog2(5) == 3
-        assert clog2(8) == 3
-        assert clog2(9) == 4
-        assert clog2(16) == 4
-        assert clog2(17) == 5
-        assert clog2(32) == 5
-        assert clog2(33) == 6
-        assert clog2(64) == 6
-        assert clog2(128) == 7
-        assert clog2(256) == 8
-        assert clog2(1024) == 10
-
-    def test_is_pow2_true_cases(self):
-        """Test is_pow2 returns True for powers of 2."""
-        assert is_pow2(1) is True
-        assert is_pow2(2) is True
-        assert is_pow2(4) is True
-        assert is_pow2(8) is True
-        assert is_pow2(16) is True
-        assert is_pow2(32) is True
-        assert is_pow2(64) is True
-        assert is_pow2(128) is True
-        assert is_pow2(256) is True
-        assert is_pow2(512) is True
-        assert is_pow2(1024) is True
-
-    def test_is_pow2_false_cases(self):
-        """Test is_pow2 returns False for non-powers of 2."""
-        assert is_pow2(0) is False
-        assert is_pow2(3) is False
-        assert is_pow2(5) is False
-        assert is_pow2(6) is False
-        assert is_pow2(7) is False
-        assert is_pow2(9) is False
-        assert is_pow2(10) is False
-        assert is_pow2(15) is False
-        assert is_pow2(17) is False
-        assert is_pow2(100) is False
-        assert is_pow2(255) is False
-        assert is_pow2(1000) is False
-
-    def test_roundup_pow2_already_power_of_2(self):
-        """Test roundup_pow2 with values that are already powers of 2."""
-        assert roundup_pow2(1) == 1
-        assert roundup_pow2(2) == 2
-        assert roundup_pow2(4) == 4
-        assert roundup_pow2(8) == 8
-        assert roundup_pow2(16) == 16
-        assert roundup_pow2(32) == 32
-        assert roundup_pow2(64) == 64
-        assert roundup_pow2(128) == 128
-        assert roundup_pow2(256) == 256
-
-    def test_roundup_pow2_non_power_of_2(self):
-        """Test roundup_pow2 with values that are not powers of 2."""
-        assert roundup_pow2(3) == 4
-        assert roundup_pow2(5) == 8
-        assert roundup_pow2(6) == 8
-        assert roundup_pow2(7) == 8
-        assert roundup_pow2(9) == 16
-        assert roundup_pow2(15) == 16
-        assert roundup_pow2(17) == 32
-        assert roundup_pow2(31) == 32
-        assert roundup_pow2(33) == 64
-        assert roundup_pow2(100) == 128
-        assert roundup_pow2(255) == 256
-        assert roundup_pow2(257) == 512
 
 
 class TestGetIndexedPath:
     """Test get_indexed_path function."""
 
-    def test_simple_path(self, compile_rdl):
+    def test_simple_path(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
         """Test simple path without arrays."""
         rdl_source = """
         addrmap my_addrmap {
@@ -111,7 +29,7 @@ class TestGetIndexedPath:
         path = get_indexed_path(top, reg_node)
         assert path == "my_reg"
 
-    def test_nested_path(self, compile_rdl):
+    def test_nested_path(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
         """Test nested path without arrays."""
         rdl_source = """
         addrmap inner_map {
@@ -143,7 +61,7 @@ class TestGetIndexedPath:
         path = get_indexed_path(top, reg_node)
         assert path == "inner.my_reg"
 
-    def test_array_path(self, compile_rdl):
+    def test_array_path(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
         """Test path with array indices."""
         rdl_source = """
         addrmap my_addrmap {
@@ -163,7 +81,7 @@ class TestGetIndexedPath:
         path = get_indexed_path(top, reg_node)
         assert path == "my_reg[i0]"
 
-    def test_multidimensional_array_path(self, compile_rdl):
+    def test_multidimensional_array_path(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
         """Test path with multidimensional arrays."""
         rdl_source = """
         addrmap my_addrmap {
@@ -183,7 +101,7 @@ class TestGetIndexedPath:
         path = get_indexed_path(top, reg_node)
         assert path == "my_reg[i0][i1]"
 
-    def test_nested_array_path(self, compile_rdl):
+    def test_nested_array_path(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
         """Test path with nested arrays."""
         rdl_source = """
         addrmap inner_map {
@@ -215,7 +133,7 @@ class TestGetIndexedPath:
         path = get_indexed_path(top, reg_node)
         assert path == "inner[i0].my_reg[i1]"
 
-    def test_custom_indexer(self, compile_rdl):
+    def test_custom_indexer(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
         """Test path with custom indexer name."""
         rdl_source = """
         addrmap my_addrmap {
@@ -235,7 +153,7 @@ class TestGetIndexedPath:
         path = get_indexed_path(top, reg_node, indexer="idx")
         assert path == "my_reg[idx0]"
 
-    def test_skip_kw_filter(self, compile_rdl):
+    def test_skip_kw_filter(self, compile_rdl: Callable[..., AddrmapNode]) -> None:
         """Test path with keyword filtering skipped."""
         rdl_source = """
         addrmap my_addrmap {

tests/utils/test_math_utils.py

@@ -0,0 +1,79 @@
+from peakrdl_busdecoder.utils import clog2, is_pow2, roundup_pow2
+
+
+class TestMathUtils:
+    """Test mathematical utility functions."""
+
+    def test_clog2_basic(self) -> None:
+        """Test clog2 function with basic values."""
+        assert clog2(1) == 0
+        assert clog2(2) == 1
+        assert clog2(3) == 2
+        assert clog2(4) == 2
+        assert clog2(5) == 3
+        assert clog2(8) == 3
+        assert clog2(9) == 4
+        assert clog2(16) == 4
+        assert clog2(17) == 5
+        assert clog2(32) == 5
+        assert clog2(33) == 6
+        assert clog2(64) == 6
+        assert clog2(128) == 7
+        assert clog2(256) == 8
+        assert clog2(1024) == 10
+
+    def test_is_pow2_true_cases(self) -> None:
+        """Test is_pow2 returns True for powers of 2."""
+        assert is_pow2(1) is True
+        assert is_pow2(2) is True
+        assert is_pow2(4) is True
+        assert is_pow2(8) is True
+        assert is_pow2(16) is True
+        assert is_pow2(32) is True
+        assert is_pow2(64) is True
+        assert is_pow2(128) is True
+        assert is_pow2(256) is True
+        assert is_pow2(512) is True
+        assert is_pow2(1024) is True
+
+    def test_is_pow2_false_cases(self) -> None:
+        """Test is_pow2 returns False for non-powers of 2."""
+        assert is_pow2(0) is False
+        assert is_pow2(3) is False
+        assert is_pow2(5) is False
+        assert is_pow2(6) is False
+        assert is_pow2(7) is False
+        assert is_pow2(9) is False
+        assert is_pow2(10) is False
+        assert is_pow2(15) is False
+        assert is_pow2(17) is False
+        assert is_pow2(100) is False
+        assert is_pow2(255) is False
+        assert is_pow2(1000) is False
+
+    def test_roundup_pow2_already_power_of_2(self) -> None:
+        """Test roundup_pow2 with values that are already powers of 2."""
+        assert roundup_pow2(1) == 1
+        assert roundup_pow2(2) == 2
+        assert roundup_pow2(4) == 4
+        assert roundup_pow2(8) == 8
+        assert roundup_pow2(16) == 16
+        assert roundup_pow2(32) == 32
+        assert roundup_pow2(64) == 64
+        assert roundup_pow2(128) == 128
+        assert roundup_pow2(256) == 256
+
+    def test_roundup_pow2_non_power_of_2(self) -> None:
+        """Test roundup_pow2 with values that are not powers of 2."""
+        assert roundup_pow2(3) == 4
+        assert roundup_pow2(5) == 8
+        assert roundup_pow2(6) == 8
+        assert roundup_pow2(7) == 8
+        assert roundup_pow2(9) == 16
+        assert roundup_pow2(15) == 16
+        assert roundup_pow2(17) == 32
+        assert roundup_pow2(31) == 32
+        assert roundup_pow2(33) == 64
+        assert roundup_pow2(100) == 128
+        assert roundup_pow2(255) == 256
+        assert roundup_pow2(257) == 512

tools/shims/xargs

@@ -0,0 +1,61 @@
+#!/usr/bin/env python3
+
+"""Minimal xargs replacement for environments where /usr/bin/xargs is unavailable.
+
+Supports the subset of functionality exercised by Verilator's generated makefiles:
+optional -0 (NUL-delimited input) and -t (echo command) flags, followed by a command
+invocation constructed from stdin tokens.
+"""
+
+from __future__ import annotations
+
+import subprocess
+import sys
+
+
+def main() -> int:
+    args = sys.argv[1:]
+    show_cmd = False
+    null_delimited = False
+
+    while args and args[0].startswith("-") and args[0] != "-":
+        opt = args.pop(0)
+        if opt == "-0":
+            null_delimited = True
+        elif opt == "-t":
+            show_cmd = True
+        else:
+            sys.stderr.write(f"xargs shim: unsupported option {opt}\n")
+            return 1
+
+    if not args:
+        args = ["echo"]
+
+    data = sys.stdin.buffer.read()
+    if not data.strip():
+        return 0
+
+    if null_delimited:
+        items = [chunk.decode() for chunk in data.split(b"\0") if chunk]
+    else:
+        items = data.decode().split()
+
+    if not items:
+        return 0
+
+    cmd = args + items
+    if show_cmd:
+        print(" ".join(cmd))
+
+    try:
+        subprocess.check_call(cmd)
+    except FileNotFoundError:
+        return 127
+    except subprocess.CalledProcessError as exc:
+        return exc.returncode
+
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())