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base: bslathi19:31513dc16a766678a415ffa70438e2fae74a31f9
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bslathi19:master bslathi19:reorg
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compare: bslathi19:reorg
Branches Tags
bslathi19:master bslathi19:reorg

9 Commits
31513dc16a ... reorg

Author SHA1 Message Date
Byron Lathi
e702967e8e Get it all working again 2025-11-22 23:02:55 -08:00
Byron Lathi
d9a25d0a7a Get it kind of working again 2025-11-22 17:02:25 -08:00
Byron Lathi
85cb3cc2a6 Use taxi apb interface, finish reorg 2025-11-22 16:07:56 -08:00
Byron Lathi
de33a46c78 reorg 2025-11-22 12:30:57 -08:00
Byron Lathi
0de33aaa1b Get it to compile 2025-11-16 23:15:46 -08:00
Byron Lathi
cc40760c66 Change from using the value of the macro to just an ifdef 2025-11-15 15:51:14 -08:00
Byron Lathi
462a3cb158 Fix gty ip path 2025-11-15 15:44:26 -08:00
Byron Lathi
d32d31cead Add basic tb that shows it kind of works 2025-11-15 15:42:09 -08:00
Byron Lathi
4bd09e8f83 Add eth dma wrapper 2025-11-15 14:37:25 -08:00
42 changed files with 4795 additions and 220 deletions
Expand all files Collapse all files

10
.gitignore vendored
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@@ -2,4 +2,12 @@
.venv/
sim_build/
__pycache__/
__pycache__/
clockInfo.txt
vivado.*
tight_setup_hold_pins.txt
*.log
cong/
nonprojectflow/

2
.gitmodules vendored
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@@ -1,3 +1,3 @@
[submodule "sub/taxi"]
path = sub/taxi
url = https://github.com/fpganinja/taxi.git
url = ../taxi.git

3
ip/taxi_eth_phy_25g_us_gty_ch/.gitignore vendored Normal file
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@@ -0,0 +1,3 @@
*
!.gitignore
!*.xci

920
ip/taxi_eth_phy_25g_us_gty_ch/taxi_eth_phy_25g_us_gty_ch.xci Normal file
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@@ -0,0 +1,920 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "taxi_eth_phy_25g_us_gty_ch",
"component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7",
"ip_revision": "19",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"GT_TYPE": [ { "value": "GTY", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_GT_PRIM_TYPE": [ { "value": "gtye4", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"GT_REV": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"GT_DIRECTION": [ { "value": "BOTH", "resolve_type": "user", "usage": "all" } ],
"RX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"TX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"CHANNEL_ENABLE": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
"TX_MASTER_CHANNEL": [ { "value": "X0Y0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_MASTER_CHANNEL": [ { "value": "X0Y0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_COMMONS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"LOCATE_COMMON": [ { "value": "EXAMPLE_DESIGN", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_NUM_COMMONS_CORE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ],
"RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"INS_LOSS_NYQ": [ { "value": "20", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_LINE_RATE": [ { "value": "25.78125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"TX_DATA_ENCODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_INT_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TX_QPLL_FRACN_NUMERATOR": [ { "value": "8388608", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TX_OUTCLK_SOURCE": [ { "value": "TXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
"RX_LINE_RATE": [ { "value": "25.78125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_PLL_TYPE": [ { "value": "QPLL0", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_FREQUENCY": [ { "value": "156.25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_DATA_DECODING": [ { "value": "64B66B_ASYNC", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_USER_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_INT_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_QPLL_FRACN_NUMERATOR": [ { "value": "8388608", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_EQ_MODE": [ { "value": "DFE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_JTOL_FC": [ { "value": "10", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_OUTCLK_SOURCE": [ { "value": "RXPROGDIVCLK", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
"RX_TERMINATION_PROG_VALUE": [ { "value": "800", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_COUPLING": [ { "value": "AC", "resolve_type": "user", "usage": "all" } ],
"RX_BUFFER_BYPASS_MODE": [ { "value": "MULTI", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_CB_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_COMMAALIGN": [ { "value": "DISABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "usage": "all" } ],
"TX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "usage": "all" } ],
"RESET_SEQUENCE_INTERVAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RX_COMMA_PRESET": [ { "value": "NONE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_VALID_ONLY": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_COMMA_P_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_M_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_DOUBLE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_COMMA_P_VAL": [ { "value": "0101111100", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_M_VAL": [ { "value": "1010000011", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_MASK": [ { "value": "0000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_COMMA_ALIGN_WORD": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RX_SLIDE_MODE": [ { "value": "OFF", "resolve_type": "user", "usage": "all" } ],
"RX_CB_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MAX_SKEW": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MAX_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CB_MASK": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_VAL": [ { "value": "00000000000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_K": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_DISP": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_0_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_MASK_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CB_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CB_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_KEEP_IDLE": [ { "value": "DISABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_PRECEDENCE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_REPEAT_WAIT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"RX_CC_MASK": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_VAL": [ { "value": "00000000000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "user", "usage": "all" } ],
"RX_CC_K": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_DISP": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_0_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_0_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_0": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_1": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_1": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_2": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_2": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_MASK_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"ENABLE_OPTIONAL_PORTS": [ { "value": "gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out txpd_in txpdelecidlemode_in rxpd_in txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in txpolarity_in rxpolarity_in txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in rxcdrlock_out rxcdrhold_in rxcdrovrden_in rxlpmen_in", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_SOURCE": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_SOURCE": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"LOCATE_RESET_CONTROLLER": [ { "value": "EXAMPLE_DESIGN", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"LOCATE_TX_BUFFER_BYPASS_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"LOCATE_RX_BUFFER_BYPASS_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"LOCATE_IN_SYSTEM_IBERT_CORE": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
"LOCATE_TX_USER_CLOCKING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"C_TXPROGDIV_FREQ_VAL": [ { "value": "390.625", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_BUFFBYPASS_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_DATA_ENCODING": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_TX_MASTER_CHANNEL_IDX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_PLL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USRCLK_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USRCLK2_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexuplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku3p" } ],
"PACKAGE": [ { "value": "ffvb676" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "19" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"gtwiz_userclk_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_done_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_done_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"eyescanreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"gtrxreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"gttxreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"gtyrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtyrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll0refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1clk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1refclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxcdrhold_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxcdrovrden_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxdfelpmreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxgearboxslip_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxlpmen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxpd_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxpllclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x3" } ],
"rxpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxprogdivreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxsysclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x2" } ],
"rxuserrdy_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
"txdiffctrl_in": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x18" } ],
"txelecidle_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txheader_in": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"txinhibit_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txmaincursor_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x50" } ],
"txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpd_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"txpdelecidlemode_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpllclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x3" } ],
"txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpostcursor_in": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ],
"txprecursor_in": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ],
"txprogdivreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txsequence_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
"txsysclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x2" } ],
"txuserrdy_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
"gtpowergood_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtytxn_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtytxp_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxcdrlock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxdatavalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxheader_out": [ { "direction": "out", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"rxheadervalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxstartofseq_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"txpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
}
}
}
}

124
ip/taxi_eth_phy_25g_us_gty_full/taxi_eth_phy_25g_us_gty_full.xci
View File

@@ -13,10 +13,10 @@
"GT_DIRECTION": [ { "value": "BOTH", "resolve_type": "user", "usage": "all" } ],
"RX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"TX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ],
"CHANNEL_ENABLE": [ { "value": "X0Y15 X0Y14", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TX_MASTER_CHANNEL": [ { "value": "X0Y15", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_MASTER_CHANNEL": [ { "value": "X0Y15", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"CHANNEL_ENABLE": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
"TX_MASTER_CHANNEL": [ { "value": "X0Y0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_MASTER_CHANNEL": [ { "value": "X0Y0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_TOTAL_NUM_COMMONS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"LOCATE_COMMON": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_NUM_COMMONS_CORE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -155,7 +155,7 @@
"RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"ENABLE_OPTIONAL_PORTS": [ { "value": "eyescanreset_in gtrefclk01_in pcierateqpll0_in pcierateqpll1_in qpll0pd_in qpll1pd_in qpll1reset_in rxcdrhold_in rxcdrovrden_in rxdfelpmreset_in rxlpmen_in rxpcsreset_in rxpd_in rxpllclksel_in rxpmareset_in rxpolarity_in rxsysclksel_in txdiffctrl_in txelecidle_in txinhibit_in txmaincursor_in txpcsreset_in txpd_in txpdelecidlemode_in txpllclksel_in txpmareset_in txpolarity_in txpostcursor_in txprecursor_in txsysclksel_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"ENABLE_OPTIONAL_PORTS": [ { "value": "qpll0reset_in qpll1reset_in qpll0pd_in qpll1pd_in gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out pcierateqpll0_in pcierateqpll1_in gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out txpd_in txpdelecidlemode_in rxpd_in txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in txpolarity_in rxpolarity_in txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in rxcdrlock_out rxcdrhold_in rxcdrovrden_in rxlpmen_in", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"RX_REFCLK_SOURCE": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"TX_REFCLK_SOURCE": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
"RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
@@ -166,11 +166,11 @@
"LOCATE_TX_USER_CLOCKING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"LOCATE_RX_USER_CLOCKING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "usage": "all" } ],
"ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"PRESET": [ { "value": "GTY-10GBASE-R", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PRESET": [ { "value": "10GBASE-R", "resolve_type": "user", "usage": "all" } ],
"INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "18", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "16", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
"INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -728,7 +728,7 @@
"Component_Name": [ { "value": "taxi_eth_phy_25g_us_gty_full", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_CHANNEL_ENABLE": [ { "value": "\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_CHANNEL_ENABLE": [ { "value": "\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_PCIE_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -775,7 +775,7 @@
"C_RX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_INT_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_LINE_RATE": [ { "value": "25.78125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_MASTER_CHANNEL_IDX": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_MASTER_CHANNEL_IDX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RX_OUTCLK_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_RX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -793,7 +793,7 @@
"C_RX_USRCLK2_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_SECONDARY_QPLL_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TOTAL_NUM_CHANNELS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TOTAL_NUM_COMMONS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TOTAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TXPROGDIV_FREQ_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -806,7 +806,7 @@
"C_TX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_INT_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_LINE_RATE": [ { "value": "25.78125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_MASTER_CHANNEL_IDX": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_MASTER_CHANNEL_IDX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_FREQUENCY": [ { "value": "390.6250000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -859,8 +859,8 @@
"gtwiz_userclk_rx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_done_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_done_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtrefclk00_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtrefclk01_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"pcierateqpll0_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
@@ -875,55 +875,55 @@
"qpll1lock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1outclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1outrefclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"eyescanreset_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"gtrxreset_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"gttxreset_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"gtyrxn_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"gtyrxp_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxcdrhold_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxcdrovrden_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxdfelpmreset_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxgearboxslip_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxlpmen_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxpcsreset_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxpd_in": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"rxpllclksel_in": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x3" } ],
"rxpmareset_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxpolarity_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxprogdivreset_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxsysclksel_in": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x2" } ],
"rxuserrdy_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
"txdiffctrl_in": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0x18" } ],
"txelecidle_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
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"txinhibit_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
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"txpd_in": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"txpdelecidlemode_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
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}
}
}

3
ip/taxi_eth_phy_25g_us_gty_ll_ch/.gitignore vendored Normal file
View File

@@ -0,0 +1,3 @@
*
!.gitignore
!*.xci

928
ip/taxi_eth_phy_25g_us_gty_ll_ch/taxi_eth_phy_25g_us_gty_ll_ch.xci Normal file
View File

@@ -0,0 +1,928 @@
{
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"component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7",
"ip_revision": "19",
"gen_directory": ".",
"parameters": {
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3
ip/taxi_eth_phy_25g_us_gty_ll_full/.gitignore vendored Normal file
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938
ip/taxi_eth_phy_25g_us_gty_ll_full/taxi_eth_phy_25g_us_gty_ll_full.xci Normal file
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"C_TX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_INT_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_LINE_RATE": [ { "value": "25.78125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_MASTER_CHANNEL_IDX": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_OUTCLK_FREQUENCY": [ { "value": "402.8320312", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_OUTCLK_SOURCE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_PLL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USER_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TX_USRCLK_FREQUENCY": [ { "value": "402.8320312", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_TX_USRCLK2_FREQUENCY": [ { "value": "402.8320312", "resolve_type": "generated", "format": "float", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintexuplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcku3p" } ],
"PACKAGE": [ { "value": "ffvb676" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "19" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2024.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"gtwiz_userclk_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_tx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_srcclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_usrclk2_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userclk_rx_active_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_tx_start_user_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_tx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_tx_error_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_rx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_rx_start_user_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_buffbypass_rx_error_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_tx_done_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_reset_rx_done_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
"gtrefclk00_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtrefclk01_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"pcierateqpll0_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"pcierateqpll1_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"qpll0pd_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll0reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"qpll1pd_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
"qpll1reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
"qpll0lock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0outclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll0outrefclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1lock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1outclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"qpll1outrefclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"eyescanreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"gtrxreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"gttxreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"gtyrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtyrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxcdrhold_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxcdrovrden_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxdfelpmreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxgearboxslip_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxlpmen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxpd_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"rxpllclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x3" } ],
"rxpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxprogdivreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"rxsysclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x2" } ],
"rxuserrdy_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
"txdiffctrl_in": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x18" } ],
"txelecidle_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txheader_in": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"txinhibit_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txmaincursor_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0x50" } ],
"txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpd_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
"txpdelecidlemode_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpllclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x3" } ],
"txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txpostcursor_in": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ],
"txprecursor_in": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ],
"txprogdivreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"txsequence_in": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
"txsysclksel_in": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x2" } ],
"txuserrdy_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ],
"gtpowergood_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtytxn_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"gtytxp_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxcdrlock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxdatavalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxheader_out": [ { "direction": "out", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
"rxheadervalid_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"rxstartofseq_out": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
"txpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txprgdivresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"txresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
}
}
}
}

2
requirements.txt
View File

@@ -7,4 +7,4 @@ rtl-manifest
build_fpga
fpga-sim
peakrdl
git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@taxi_apb

87
sim/alibaba_pcie.py
View File

@@ -8,6 +8,8 @@ from cocotbext.axi import AxiStreamBus
from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
from baser import BaseRSerdesSource, BaseRSerdesSink
CLK_PERIOD = 4
class TB:
@@ -74,26 +76,61 @@ class TB:
pf3_msix_pba_offset=0x00000000,
# signals
user_clk=dut.clk_250,
user_reset=dut.rst_250,
user_lnk_up=dut.user_lnk_up,
user_clk=dut.u_pcie_top.clk_250,
user_reset=dut.u_pcie_top.rst_250,
user_lnk_up=dut.u_pcie_top.user_lnk_up,
rq_bus=AxiStreamBus.from_entity(dut.s_axis_rq),
rc_bus=AxiStreamBus.from_entity(dut.m_axis_rc),
cq_bus=AxiStreamBus.from_entity(dut.m_axis_cq),
cc_bus=AxiStreamBus.from_entity(dut.s_axis_cc),
rq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_rq),
rc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_rc),
cq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_cq),
cc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_cc),
)
self.dev.functions[0].configure_bar(0, 64*1024)
self.rc.make_port().connect(self.dev)
cocotb.start_soon(Clock(dut.sfp_mgt_clk_p, 6.4, units="ns").start())
self.serdes_sources = []
self.serdes_sinks = []
for ch in dut.u_eth_dma_wrapper.u_taxi_eth_phy_25g_us.ch:
gt_inst = ch.ch_inst.gt.gt_inst
clk = 2.56
gbx_cfg = None
cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
self.serdes_sources.append(BaseRSerdesSource(
data=gt_inst.serdes_rx_data,
data_valid=gt_inst.serdes_rx_data_valid,
hdr=gt_inst.serdes_rx_hdr,
hdr_valid=gt_inst.serdes_rx_hdr_valid,
clock=gt_inst.rx_clk,
slip=gt_inst.serdes_rx_bitslip,
reverse=True,
gbx_cfg=gbx_cfg
))
self.serdes_sinks.append(BaseRSerdesSink(
data=gt_inst.serdes_tx_data,
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg
))
@cocotb.test
async def test_sanity(dut):
tb = TB(dut)
await FallingEdge(dut.rst_250)
await Timer(100, 'ns')
await Timer(10, 'us')
await tb.rc.enumerate()
@@ -105,28 +142,50 @@ async def test_sanity(dut):
dev_bar0 = dev.bar_window[0]
tb.log.info(dev_bar0.write)
message = b"Hello, world! This is a long string of data with many letters and words."
await mem.write(0, message)
# DMA from host to dma memory
await dev_bar0.write_dword(0x0, 0x00000000)
await dev_bar0.write_dword(0x4, 0x00000000)
await dev_bar0.write_dword(0x8, 0x00000000)
await dev_bar0.write_dword(0xc, len(message))
await dev_bar0.write_dword(0x10, 0x00000001)
await Timer(100, "ns")
await Timer(1, "us")
# Set up stream to memory DMA to store ethernet frame
await dev_bar0.write_dword(0x180, 0x00000000)
await dev_bar0.write_dword(0x184, 0x00000000)
await dev_bar0.write_dword(0x188, 0x00000000)
await dev_bar0.write_dword(0x18c, len(message))
await dev_bar0.write_dword(0x190, 0x00000001)
# Trigger memory to stream dma to send ethernet frame
await dev_bar0.write_dword(0x1a0, 0x00000000)
await dev_bar0.write_dword(0x1a4, 0x00000000)
await dev_bar0.write_dword(0x1a8, 0x00000000)
await dev_bar0.write_dword(0x1ac, len(message))
await dev_bar0.write_dword(0x1b0, 0x00000001)
rx_frame = await tb.serdes_sinks[0].recv()
tb.log.info(rx_frame)
await tb.serdes_sources[1].send(rx_frame)
await Timer(1, "us")
# DMA from dma memory to host
await dev_bar0.write_dword(0x20, 0x00000100)
await dev_bar0.write_dword(0x24, 0x00000000)
await dev_bar0.write_dword(0x28, 0x00000000)
await dev_bar0.write_dword(0x2c, len(message))
await dev_bar0.write_dword(0x30, 0x00000001)
await Timer(10, "us")
await Timer(1, "us")
read_msg = await mem.read(0x100, len(message))
msg = await mem.read(0x100, len(message))
tb.log.info(read_msg)
tb.log.info(msg)

2
sim/alibaba_pcie.yaml
View File

@@ -7,4 +7,4 @@ tests:
waves: True
defines:
SIM: ""
SIM: "1"

22
sources.list
View File

@@ -1,9 +1,17 @@
ip/pcie4_uscale_plus_0/pcie4_uscale_plus_0.xci
ip/taxi_eth_phy_25g_us_gty_25g_156/taxi_eth_phy_25g_us_gty_25g_156.xci
src/alibaba_cloud.xdc
src/alibaba_pcie_top.sv
src/regs/verilator.vlt
src/regs/pcie_dma_regs_pkg.sv
src/regs/pcie_dma_regs.sv
src/pcie_dma_wrapper.sv
ip/taxi_eth_phy_25g_us_gty_ch/taxi_eth_phy_25g_us_gty_ch.xci
ip/taxi_eth_phy_25g_us_gty_full/taxi_eth_phy_25g_us_gty_full.xci
ip/taxi_eth_phy_25g_us_gty_ll_ch/taxi_eth_phy_25g_us_gty_ll_ch.xci
ip/taxi_eth_phy_25g_us_gty_ll_full/taxi_eth_phy_25g_us_gty_ll_full.xci
sub/taxi_sources.list
src/pcie/sources.list
src/eth/sources.list
src/regs/verilator.vlt
src/regs/alibaba_pcie_top_regs_pkg.sv
src/regs/alibaba_pcie_top_regs.sv
src/alibaba_pcie_top.sv
src/alibaba_cloud.xdc

13
src/alibaba_cloud.xdc
View File

@@ -51,4 +51,17 @@ set_property -dict {LOC AD2} [get_ports {pci_exp_rxp[5]}]
set_property -dict {LOC AE4} [get_ports {pci_exp_rxp[6]}]
set_property -dict {LOC AF2} [get_ports {pci_exp_rxp[7]}]
set_property -dict {LOC B6} [get_ports {sfp_txn[0]}]
set_property -dict {LOC B7} [get_ports {sfp_txp[0]}]
set_property -dict {LOC A3} [get_ports {sfp_rxn[0]}]
set_property -dict {LOC A4} [get_ports {sfp_rxp[0]}]
set_property -dict {LOC D6} [get_ports {sfp_txn[1]}]
set_property -dict {LOC D7} [get_ports {sfp_txp[1]}]
set_property -dict {LOC B1} [get_ports {sfp_rxn[1]}]
set_property -dict {LOC B2} [get_ports {sfp_rxp[1]}]
set_property -dict {LOC K7} [get_ports {sfp_mgt_clk_p}]
set_property -dict {LOC K6} [get_ports {sfp_mgt_clk_n}]
set_property -dict {LOC A9 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]

171
src/alibaba_pcie_top.sv
View File

@@ -20,70 +20,46 @@
//////////////////////////////////////////////////////////////////////////////////
module alibaba_pcie(
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [7:0] pci_exp_txp,
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [7:0] pci_exp_txp,
output wire [7:0] pci_exp_txn,
output wire [3:0] Led_o,
input wire pcie_mgt_refclk_p,
input wire pcie_mgt_refclk_n,
input wire pcie_mgt_refclk_p,
input wire pcie_mgt_refclk_n,
input wire pcie_reset_n,
input wire pcie_reset_n
input wire sfp_mgt_clk_p,
input wire sfp_mgt_clk_n,
output wire sfp_txp [2],
output wire sfp_txn [2],
input wire sfp_rxp [2],
input wire sfp_rxn [2],
output wire [3:0] Led_o
);
logic clk_pcie_gt;
logic clk_pcie;
logic rst_pcie;
logic clk_250;
logic rst_250;
logic user_lnk_up;
logic phy_rdy_out;
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(62), .KEEP_W(8)) s_axis_rq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
taxi_axil_if m_axil_rd();
taxi_axil_if m_axil_wr();
taxi_apb_if #(.ADDR_W(6)) m_apb();
taxi_apb_if #(.ADDR_W(alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)) s_apb();
`ifndef SIM
IBUFDS_GTE4 m_ibufds (
.CEB('0),
.I(pcie_mgt_refclk_p),
.IB(pcie_mgt_refclk_n),
.O(clk_pcie_gt),
.ODIV2(clk_pcie)
);
`endif
taxi_apb_if #(.ADDR_W(pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)) pcie_apb();
taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_apb();
assign Led_o[0] = user_lnk_up;
assign Led_o[1] = phy_rdy_out;
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
.clk (clk_250),
.rst (rst_250),
.s_axis_cq (m_axis_cq),
.m_axis_cc (s_axis_cc),
.m_axil_wr (m_axil_wr),
.m_axil_rd (m_axil_rd),
.completer_id ('0),
.completer_id_en ('0),
.stat_err_cor (),
.stat_err_uncor ()
alibaba_pcie_top_regs u_alibaba_pcie_top_regs (
.s_apb (s_apb),
.m_apb_pcie_top_regs (pcie_apb),
.m_apb_eth_dma_wrapper_regs (eth_apb)
);
taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
@@ -93,83 +69,52 @@ taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
.s_axil_wr (m_axil_wr),
.s_axil_rd (m_axil_rd),
.m_apb (m_apb)
.m_apb (s_apb)
);
pcie_dma_wrapper u_pcie_dma_wrapper (
.clk (clk_250),
.rst (rst_250),
.m_axis_rq (s_axis_rq),
.s_axis_rc (m_axis_rc),
eth_dma_wrapper u_eth_dma_wrapper (
.clk_250 (clk_250),
.rst_250 (rst_250),
.s_apb (m_apb)
.sfp_mgt_clk_p (sfp_mgt_clk_p),
.sfp_mgt_clk_n (sfp_mgt_clk_n),
.sfp_txp (sfp_txp),
.sfp_txn (sfp_txn),
.sfp_rxp (sfp_rxp),
.sfp_rxn (sfp_rxn),
.wr_dma_mst (dma_ram_eth_wr_if),
.rd_dma_mst (dma_ram_eth_rd_if),
.s_apb (eth_apb)
);
`ifndef SIM
pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
.pci_exp_txn(pci_exp_txn),
.pci_exp_txp(pci_exp_txp),
.pci_exp_rxn(pci_exp_rxn),
.pci_exp_rxp(pci_exp_rxp),
pcie_top u_pcie_top(
.pci_exp_rxp (pci_exp_rxp),
.pci_exp_rxn (pci_exp_rxn),
.pci_exp_txp (pci_exp_txp),
.pci_exp_txn (pci_exp_txn),
.user_clk(clk_250),
.user_reset(rst_250),
.user_lnk_up(user_lnk_up),
.pcie_mgt_refclk_p (pcie_mgt_refclk_p),
.pcie_mgt_refclk_n (pcie_mgt_refclk_n),
.s_axis_rq_tdata(s_axis_rq.tdata),
.s_axis_rq_tkeep(s_axis_rq.tkeep),
.s_axis_rq_tlast(s_axis_rq.tlast),
.s_axis_rq_tready(s_axis_rq.tready),
.s_axis_rq_tuser(s_axis_rq.tuser),
.s_axis_rq_tvalid(s_axis_rq.tvalid),
.pcie_reset_n (pcie_reset_n),
.m_axis_rc_tdata(m_axis_rc.tdata),
.m_axis_rc_tkeep(m_axis_rc.tkeep),
.m_axis_rc_tlast(m_axis_rc.tlast),
.m_axis_rc_tready(m_axis_rc.tready),
.m_axis_rc_tuser(m_axis_rc.tuser),
.m_axis_rc_tvalid(m_axis_rc.tvalid),
.user_lnk_up (Led_o[0]),
.phy_rdy_out (Led_o[1]),
.m_axis_cq_tdata(m_axis_cq.tdata),
.m_axis_cq_tkeep(m_axis_cq.tkeep),
.m_axis_cq_tlast(m_axis_cq.tlast),
.m_axis_cq_tready(m_axis_cq.tready),
.m_axis_cq_tuser(m_axis_cq.tuser),
.m_axis_cq_tvalid(m_axis_cq.tvalid),
.o_clk_250 (clk_250),
.o_rst_250 (rst_250),
.s_axis_cc_tdata(s_axis_cc.tdata),
.s_axis_cc_tkeep(s_axis_cc.tkeep),
.s_axis_cc_tlast(s_axis_cc.tlast),
.s_axis_cc_tready(s_axis_cc.tready),
.s_axis_cc_tuser(s_axis_cc.tuser),
.s_axis_cc_tvalid(s_axis_cc.tvalid),
.dma_ram_eth_wr_if (dma_ram_eth_wr_if),
.dma_ram_eth_rd_if (dma_ram_eth_rd_if),
.cfg_interrupt_int('0),
.cfg_interrupt_pending(),
.cfg_interrupt_sent('0),
.cfg_interrupt_msi_enable(),
.cfg_interrupt_msi_mmenable(),
.cfg_interrupt_msi_mask_update(),
.cfg_interrupt_msi_data(),
.cfg_interrupt_msi_select('0),
.cfg_interrupt_msi_int('0),
.cfg_interrupt_msi_pending_status('0),
.cfg_interrupt_msi_pending_status_data_enable('0),
.cfg_interrupt_msi_pending_status_function_num('0),
.cfg_interrupt_msi_sent(),
.cfg_interrupt_msi_fail(),
.cfg_interrupt_msi_attr('0),
.cfg_interrupt_msi_tph_present('0),
.cfg_interrupt_msi_tph_type('0),
.cfg_interrupt_msi_tph_st_tag('0),
.cfg_interrupt_msi_function_number('0),
.m_axil_rd (m_axil_rd),
.m_axil_wr (m_axil_wr),
.sys_clk(clk_pcie),
.sys_clk_gt(clk_pcie_gt),
.sys_reset(pcie_reset_n),
.phy_rdy_out(phy_rdy_out)
.s_apb (pcie_apb)
);
`endif
endmodule

468
src/eth/eth_dma_wrapper.sv Normal file
View File

@@ -0,0 +1,468 @@
module eth_dma_wrapper (
input wire clk_250,
input wire rst_250,
input sfp_mgt_clk_p,
input sfp_mgt_clk_n,
output wire sfp_txp [2],
output wire sfp_txn [2],
input wire sfp_rxp [2],
input wire sfp_rxn [2],
taxi_dma_ram_if.wr_mst wr_dma_mst,
taxi_dma_ram_if.rd_mst rd_dma_mst,
taxi_apb_if.slv s_apb
);
wire mac_rx_clk[2];
wire mac_tx_clk[2];
wire mac_rx_rst[2];
wire mac_tx_rst[2];
wire sfp_mgt_refclk;
wire sfp_mgt_clk_int;
wire sfp_mgt_clk_bufg;
wire sfp_rst;
logic xcvr_gtpowergood;
`ifdef SIM
assign sfp_mgt_refclk = sfp_mgt_clk_p;
assign sfp_mgt_clk_int = sfp_mgt_clk_p;
assign sfp_mgt_clk_bufg = sfp_mgt_clk_int;
`else
IBUFDS_GTE4 ibufds_gte4_sfp_mgt_clk_inst (
.I (sfp_mgt_clk_p),
.IB (sfp_mgt_clk_n),
.CEB (1'b0),
.O (sfp_mgt_refclk),
.ODIV2 (sfp_mgt_clk_int)
);
BUFG_GT bufg_gt_sfp_mgt_clk_inst (
.CE (&xcvr_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (sfp_mgt_clk_int),
.O (sfp_mgt_clk_bufg)
);
`endif
taxi_sync_reset #(
.N(4)
)
qsfp_sync_reset_inst (
.clk(sfp_mgt_clk_bufg),
.rst(rst_250),
.out(sfp_rst)
);
taxi_axis_if #(.DATA_W(64)) axis_tx_250();
taxi_axis_if #(.DATA_W(64)) mac_tx_axis[2]();
taxi_axis_if #(.DATA_W(64)) axis_rx_250();
taxi_axis_if #(.DATA_W(64)) mac_rx_axis[2]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
generate
for (genvar i = 0; i < 2; i++) begin
taxi_axis_null_snk u_tx_cpl_stub (
.s_axis(axis_sfp_tx_cpl[i])
);
end
endgenerate
taxi_axis_if axis_sfp_stat();
taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) eth_dma_apb();
taxi_apb_if #(.ADDR_W(eth_mac_25g_us_regs_pkg::ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH)) eth_mac_apb();
eth_dma_wrapper_regs u_eth_dma_wrapper_regs (
.s_apb (s_apb),
.m_apb_eth_mac_25g_us_regs (eth_mac_apb),
.m_apb_pcie_dma_regs (eth_dma_apb)
);
eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in;
eth_mac_25g_us_regs u_eth_mac_25g_us_regs (
.clk (clk_250),
.rst (rst_250),
.s_apb_psel (eth_mac_apb.psel),
.s_apb_penable (eth_mac_apb.penable),
.s_apb_pwrite (eth_mac_apb.pwrite),
.s_apb_pprot (eth_mac_apb.pprot),
.s_apb_paddr (eth_mac_apb.paddr),
.s_apb_pwdata (eth_mac_apb.pwdata),
.s_apb_pstrb (eth_mac_apb.pstrb),
.s_apb_pready (eth_mac_apb.pready),
.s_apb_prdata (eth_mac_apb.prdata),
.s_apb_pslverr (eth_mac_apb.pslverr),
.hwif_in (hwif_in)
);
logic rx_block_lock[2];
logic rx_status[2];
logic xcvr_qpll0lock_out;
logic xcvr_qpll1lock_out;
always_comb begin
hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next = xcvr_qpll0lock_out;
hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next = xcvr_qpll1lock_out;
for (int i = 0; i < 2; i++) begin
hwif_in.lanes[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
hwif_in.lanes[i].rx_status.rx_status.next = rx_status[i];
end
end
taxi_eth_mac_25g_us #(
`ifdef SIM
.SIM('1),
`else
.SIM('0),
`endif
.VENDOR("XILINX"),
.FAMILY("kintexuplus"),
.CNT(2),
.CFG_LOW_LATENCY(0),
.GT_TYPE("GTY")
// leave all other parameters default for now
) u_taxi_eth_phy_25g_us (
.xcvr_ctrl_clk (clk_250),
.xcvr_ctrl_rst (sfp_rst),
.xcvr_gtpowergood_out (xcvr_gtpowergood),
.xcvr_gtrefclk00_in (sfp_mgt_refclk),
.xcvr_qpll0pd_in (1'b0),
.xcvr_qpll0reset_in (1'b0),
.xcvr_qpll0pcierate_in (3'd0),
.xcvr_qpll0lock_out (xcvr_qpll0lock_out),
.xcvr_qpll0clk_out (),
.xcvr_qpll0refclk_out (),
.xcvr_gtrefclk01_in (sfp_mgt_refclk),
.xcvr_qpll1pd_in (1'b0),
.xcvr_qpll1reset_in (1'b0),
.xcvr_qpll1pcierate_in (3'd0),
.xcvr_qpll1lock_out (xcvr_qpll1lock_out),
.xcvr_qpll1clk_out (),
.xcvr_qpll1refclk_out (),
.xcvr_txp (sfp_txp),
.xcvr_txn (sfp_txn),
.xcvr_rxp (sfp_rxp),
.xcvr_rxn (sfp_rxn),
.rx_clk (mac_rx_clk),
.rx_rst_in ('{2{'0}}),
.rx_rst_out (mac_rx_rst),
.tx_clk (mac_tx_clk),
.tx_rst_in ('{2{'0}}),
.tx_rst_out (mac_tx_rst),
.ptp_sample_clk ('{2{'0}}),
.s_axis_tx (mac_tx_axis), // TODO
.m_axis_tx_cpl (axis_sfp_tx_cpl), // TODO
.m_axis_rx (mac_rx_axis), // TODO
.tx_ptp_ts ('{2{'0}}),
.tx_ptp_ts_step ('{2{'0}}),
.rx_ptp_ts ('{2{'0}}),
.rx_ptp_ts_step ('{2{'0}}),
.tx_lfc_req ('{2{'0}}),
.tx_lfc_resend ('{2{'0}}),
.rx_lfc_en ('{2{'0}}),
.rx_lfc_req (),
.rx_lfc_ack ('{2{'0}}),
.tx_pfc_req ('{2{'0}}),
.tx_pfc_resend ('{2{'0}}),
.rx_pfc_en ('{2{'0}}),
.rx_pfc_req (),
.rx_pfc_ack ('{2{'0}}),
.tx_lfc_pause_en ('{2{'0}}),
.tx_pause_req ('{2{'0}}),
.tx_pause_ack (),
.stat_clk (clk_250),
.stat_rst (rst_250),
.m_axis_stat (axis_sfp_stat),
// all of these stats should really be in a registerfile
.tx_start_packet (),
.stat_tx_byte (),
.stat_tx_pkt_len (),
.stat_tx_pkt_ucast (),
.stat_tx_pkt_mcast (),
.stat_tx_pkt_bcast (),
.stat_tx_pkt_vlan (),
.stat_tx_pkt_good (),
.stat_tx_pkt_bad (),
.stat_tx_err_oversize (),
.stat_tx_err_user (),
.stat_tx_err_underflow (),
.rx_start_packet (),
.rx_error_count (),
.rx_block_lock (rx_block_lock),
.rx_high_ber (),
.rx_status (rx_status),
.stat_rx_byte (),
.stat_rx_pkt_len (),
.stat_rx_pkt_fragment (),
.stat_rx_pkt_jabber (),
.stat_rx_pkt_ucast (),
.stat_rx_pkt_mcast (),
.stat_rx_pkt_bcast (),
.stat_rx_pkt_vlan (),
.stat_rx_pkt_good (),
.stat_rx_pkt_bad (),
.stat_rx_err_oversize (),
.stat_rx_err_bad_fcs (),
.stat_rx_err_bad_block (),
.stat_rx_err_framing (),
.stat_rx_err_preamble (),
.stat_rx_fifo_drop ('{2{1'b0}}),
.stat_tx_mcf (),
.stat_rx_mcf (),
.stat_tx_lfc_pkt (),
.stat_tx_lfc_xon (),
.stat_tx_lfc_xoff (),
.stat_tx_lfc_paused (),
.stat_tx_pfc_pkt (),
.stat_tx_pfc_xon (),
.stat_tx_pfc_xoff (),
.stat_tx_pfc_paused (),
.stat_rx_lfc_pkt (),
.stat_rx_lfc_xon (),
.stat_rx_lfc_xoff (),
.stat_rx_lfc_paused (),
.stat_rx_pfc_pkt (),
.stat_rx_pfc_xon (),
.stat_rx_pfc_xoff (),
.stat_rx_pfc_paused (),
// all of these configs should really be in a registerfile
.cfg_tx_max_pkt_len ('{2{16'd1518}}),
.cfg_tx_ifg ('{2{8'd12}}),
.cfg_tx_enable ('{2{1'b1}}),
.cfg_rx_max_pkt_len ('{2{16'd1518}}),
.cfg_rx_enable ('{2{1'b1}}),
.cfg_ifg ('{2{8'd12}}),
.cfg_tx_prbs31_enable ('{2{1'b0}}),
.cfg_rx_prbs31_enable ('{2{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast ('{2{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast ('{2{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast ('{2{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast ('{2{1'b0}}),
.cfg_mcf_rx_eth_src ('{2{48'd0}}),
.cfg_mcf_rx_check_eth_src ('{2{1'b0}}),
.cfg_mcf_rx_eth_type ('{2{16'h8808}}),
.cfg_mcf_rx_opcode_lfc ('{2{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc ('{2{1'b1}}),
.cfg_mcf_rx_opcode_pfc ('{2{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc ('{2{1'b1}}),
.cfg_mcf_rx_forward ('{2{1'b0}}),
.cfg_mcf_rx_enable ('{2{1'b0}}),
.cfg_tx_lfc_eth_dst ('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src ('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type ('{2{16'h8808}}),
.cfg_tx_lfc_opcode ('{2{16'h0001}}),
.cfg_tx_lfc_en ('{2{1'b0}}),
.cfg_tx_lfc_quanta ('{2{16'hffff}}),
.cfg_tx_lfc_refresh ('{2{16'h7fff}}),
.cfg_tx_pfc_eth_dst ('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src ('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type ('{2{16'h8808}}),
.cfg_tx_pfc_opcode ('{2{16'h0101}}),
.cfg_tx_pfc_en ('{2{1'b0}}),
.cfg_tx_pfc_quanta ('{2{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh ('{2{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode ('{2{16'h0001}}),
.cfg_rx_lfc_en ('{2{1'b0}}),
.cfg_rx_pfc_opcode ('{2{16'h0101}}),
.cfg_rx_pfc_en ('{2{1'b0}})
);
taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) rd_desc();
taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) wr_desc();
pcie_dma_regs_pkg::pcie_dma_regs__in_t dma_hwif_in;
pcie_dma_regs_pkg::pcie_dma_regs__out_t dma_hwif_out;
pcie_dma_regs u_pcie_dma_regs(
.clk (clk_250),
.rst (rst_250),
.s_apb_psel (eth_dma_apb.psel),
.s_apb_penable (eth_dma_apb.penable),
.s_apb_pwrite (eth_dma_apb.pwrite),
.s_apb_pprot (eth_dma_apb.pprot),
.s_apb_paddr (eth_dma_apb.paddr),
.s_apb_pwdata (eth_dma_apb.pwdata),
.s_apb_pstrb (eth_dma_apb.pstrb),
.s_apb_pready (eth_dma_apb.pready),
.s_apb_prdata (eth_dma_apb.prdata),
.s_apb_pslverr (eth_dma_apb.pslverr),
.hwif_in (dma_hwif_in),
.hwif_out (dma_hwif_out)
);
logic [7:0] read_tag;
logic [7:0] write_tag;
always_ff @(posedge clk_250) begin
if (rst_250) begin
read_tag <= '0;
write_tag <= '0;
end else begin
if (rd_desc.req_valid && rd_desc.req_ready) begin
read_tag <= read_tag + 1;
end
if (wr_desc.req_valid && wr_desc.req_ready) begin
write_tag <= write_tag + 1;
end
end
end
always_comb begin
rd_desc.req_src_addr = dma_hwif_out.dma_rd.src_addr_low.addr.value[15:0];
rd_desc.req_src_sel = '0;
rd_desc.req_dst_addr = dma_hwif_out.dma_rd.dst_addr.addr.value;
rd_desc.req_dst_sel = '0;
rd_desc.req_imm = '0;
rd_desc.req_imm_en = '0;
rd_desc.req_len = dma_hwif_out.dma_rd.length.len.value;
rd_desc.req_tag = read_tag;
rd_desc.req_id = '0;
rd_desc.req_dest = '0;
rd_desc.req_user = '0;
rd_desc.req_valid = dma_hwif_out.dma_rd.trigger.trigger.value;
dma_hwif_in.dma_rd.trigger.trigger.hwclr = (rd_desc.req_valid && rd_desc.req_ready);
dma_hwif_in.dma_rd.done.done.hwset = rd_desc.sts_valid;
wr_desc.req_src_addr = dma_hwif_out.dma_wr.src_addr.addr.value;
wr_desc.req_src_sel = '0;
wr_desc.req_dst_addr = dma_hwif_out.dma_wr.dst_addr_low.addr.value[15:0];
wr_desc.req_dst_sel = '0;
wr_desc.req_imm = '0;
wr_desc.req_imm_en = '0;
wr_desc.req_len = dma_hwif_out.dma_wr.length.len.value;
wr_desc.req_tag = write_tag;
wr_desc.req_id = '0;
wr_desc.req_dest = '0;
wr_desc.req_user = '0;
wr_desc.req_valid = dma_hwif_out.dma_wr.trigger.trigger.value;
dma_hwif_in.dma_wr.trigger.trigger.hwclr = (wr_desc.req_valid && wr_desc.req_ready);
dma_hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
end
// 250 is too slow to actually saturate 25Gbps, but
// the DMA is not supposed to saturate it anyway
taxi_dma_client_axis_sink u_taxi_dma_client_axis_sink (
.clk (clk_250),
.rst (rst_250),
.desc_req (wr_desc),
.desc_sts (wr_desc),
.s_axis_wr_data (axis_rx_250),
.dma_ram_wr (wr_dma_mst),
.enable ('1),
.abort ('0)
);
taxi_dma_client_axis_source u_taxi_dma_client_axis_source (
.clk (clk_250),
.rst (rst_250),
.desc_req (rd_desc),
.desc_sts (rd_desc),
.m_axis_rd_data (axis_tx_250),
.dma_ram_rd (rd_dma_mst),
.enable ('1)
);
taxi_axis_async_fifo #(
.FRAME_FIFO('1)
) u_rx_async_saf (
.s_clk (mac_rx_clk[1]),
.s_rst (mac_rx_rst[1]),
.s_axis (mac_rx_axis[1]),
.m_clk (clk_250),
.m_rst (rst_250),
.m_axis (axis_rx_250),
.s_pause_req ('0),
.s_pause_ack (),
.m_pause_req ('0),
.m_pause_ack (),
.s_status_depth (),
.s_status_depth_commit (),
.s_status_overflow (),
.s_status_bad_frame (),
.s_status_good_frame (),
.m_status_depth (),
.m_status_depth_commit (),
.m_status_overflow (),
.m_status_bad_frame (),
.m_status_good_frame ()
);
taxi_axis_async_fifo #(
.FRAME_FIFO('1)
) u_tx_async_saf (
.s_clk (clk_250),
.s_rst (rst_250),
.s_axis (axis_tx_250),
.m_clk (mac_tx_clk[0]),
.m_rst (mac_tx_rst[0]),
.m_axis (mac_tx_axis[0]),
.s_pause_req ('0),
.s_pause_ack (),
.m_pause_req ('0),
.m_pause_ack (),
.s_status_depth (),
.s_status_depth_commit (),
.s_status_overflow (),
.s_status_bad_frame (),
.s_status_good_frame (),
.m_status_depth (),
.m_status_depth_commit (),
.m_status_overflow (),
.m_status_bad_frame (),
.m_status_good_frame ()
);
endmodule

2
src/eth/regs/compile_regs.sh Executable file
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@@ -0,0 +1,2 @@
peakrdl regblock -t eth_mac_25g_us_regs eth_mac_25g_us_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl -o . --cpuif taxi-apb

5
src/eth/regs/eth_dma_wrapper_regs.rdl Normal file
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@@ -0,0 +1,5 @@
addrmap eth_dma_wrapper_regs {
external eth_mac_25g_us_regs eth_mac_25g_us_regs @ 0x0;
external pcie_dma_regs pcie_dma_regs @ 0x80;
};

169
src/eth/regs/eth_dma_wrapper_regs.sv Normal file
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@@ -0,0 +1,169 @@
//==========================================================
// Module: eth_dma_wrapper_regs
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
module eth_dma_wrapper_regs (
taxi_apb_if.slv s_apb,
taxi_apb_if.mst m_apb_eth_mac_25g_us_regs,
taxi_apb_if.mst m_apb_pcie_dma_regs
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_wr_en;
logic cpuif_rd_en;
logic [7:0] cpuif_wr_addr;
logic [7:0] cpuif_rd_addr;
logic cpuif_wr_ack;
logic cpuif_wr_err;
logic [31:0] cpuif_wr_data;
logic [3:0] cpuif_wr_byte_en;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
//--------------------------------------------------------------------------
// Child instance signals
//--------------------------------------------------------------------------
typedef struct {
logic eth_mac_25g_us_regs;
logic pcie_dma_regs;
logic cpuif_err;
} cpuif_sel_t;
cpuif_sel_t cpuif_wr_sel;
cpuif_sel_t cpuif_rd_sel;
//--------------------------------------------------------------------------
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
`ifndef SYNTHESIS
initial begin
assert_bad_addr_width: assert($bits(s_apb.paddr) >= eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)
else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH);
assert_bad_data_width: assert($bits(s_apb.pwdata) == eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH);
end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
`endif
assign cpuif_req = s_apb.psel;
assign cpuif_wr_en = s_apb.pwrite;
assign cpuif_rd_en = !s_apb.pwrite;
assign cpuif_wr_addr = s_apb.paddr;
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.pstrb;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;
assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_eth_mac_25g_us_regs.psel = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs.penable = s_apb.penable;
assign m_apb_eth_mac_25g_us_regs.pwrite = cpuif_wr_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs.paddr = s_apb.paddr;
assign m_apb_eth_mac_25g_us_regs.pprot = s_apb.pprot;
assign m_apb_eth_mac_25g_us_regs.pwdata = cpuif_wr_data;
assign m_apb_eth_mac_25g_us_regs.pstrb = cpuif_wr_byte_en;
assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.penable = s_apb.penable;
assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Intermediate signals for interface array fanin
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
cpuif_rd_ack = '0;
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.eth_mac_25g_us_regs || cpuif_wr_sel.eth_mac_25g_us_regs) begin
cpuif_rd_ack = m_apb_eth_mac_25g_us_regs.pready;
cpuif_rd_err = m_apb_eth_mac_25g_us_regs.pslverr;
end
if (cpuif_rd_sel.eth_mac_25g_us_regs) begin
cpuif_rd_data = m_apb_eth_mac_25g_us_regs.prdata;
end
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
end
end
//--------------------------------------------------------------------------
// Write Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all write select signals to 0
cpuif_wr_sel = '{default: '0};
if (cpuif_req && cpuif_wr_en) begin
// A write request is pending
if ((cpuif_wr_addr < (8'h60))) begin
cpuif_wr_sel.eth_mac_25g_us_regs = 1'b1;
end
else if ((cpuif_wr_addr >= (8'h80)) && (cpuif_wr_addr < (8'hb8))) begin
cpuif_wr_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_wr_sel.cpuif_err = 1'b1;
end
end else begin
// No write request, all select signals remain 0
end
end
//--------------------------------------------------------------------------
// Read Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all read select signals to 0
cpuif_rd_sel = '{default: '0};
if (cpuif_req && cpuif_rd_en) begin
// A read request is pending
if ((cpuif_rd_addr < (8'h60))) begin
cpuif_rd_sel.eth_mac_25g_us_regs = 1'b1;
end
else if ((cpuif_rd_addr >= (8'h80)) && (cpuif_rd_addr < (8'hb8))) begin
cpuif_rd_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_rd_sel.cpuif_err = 1'b1;
end
end else begin
// No read request, all select signals remain 0
end
end
endmodule

19
src/eth/regs/eth_dma_wrapper_regs_pkg.sv Normal file
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@@ -0,0 +1,19 @@
//==========================================================
// Package: eth_dma_wrapper_regs_pkg
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
package eth_dma_wrapper_regs_pkg;
localparam ETH_DMA_WRAPPER_REGS_DATA_WIDTH = 32;
localparam ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH = 8;
localparam ETH_DMA_WRAPPER_REGS_SIZE = 'hb8;
localparam ETH_DMA_WRAPPER_REGS_ETH_MAC_25G_US_REGS_ADDR_WIDTH = 7;
localparam ETH_DMA_WRAPPER_REGS_PCIE_DMA_REGS_ADDR_WIDTH = 6;
endpackage

73
src/eth/regs/eth_mac_25g_us_regs.rdl Normal file
View File

@@ -0,0 +1,73 @@
addrmap eth_mac_25g_us_regs {
name = "";
desc = "";
regfile {
reg {
name = "xcvr_gtpowergood_out";
desc = "";
field {
name = "xcvr_gtpowergood_out";
desc = "";
hw = w;
sw = r;
} xcvr_gtpowergood_out[0:0] = 0x0;
} xcvr_gtpowergood_out @ 0x0;
reg {
name = "xcvr_qpll0lock_out";
desc = "";
field {
name = "xcvr_qpll0lock_out";
desc = "";
hw = w;
sw = r;
} xcvr_qpll0lock_out[0:0] = 0x0;
} xcvr_qpll0lock_out @ 0x4;
reg {
name = "xcvr_qpll1lock_out";
desc = "";
field {
name = "xcvr_qpll1lock_out";
desc = "";
hw = w;
sw = r;
} xcvr_qpll1lock_out[0:0] = 0x0;
} xcvr_qpll1lock_out @ 0x8;
} common @0x0;
regfile lane {
reg {
name = "rx_block_lock";
desc = "";
field {
name = "rx_block_lock";
desc = "";
hw = w;
sw = r;
} rx_block_lock[0:0] = 0x0;
} rx_block_lock @ 0x0;
reg {
name = "rx_status";
desc = "";
field {
name = "rx_status";
desc = "";
hw = w;
sw = r;
} rx_status[0:0] = 0x0;
} rx_status @ 0x4;
};
lane lanes[2] @ 0x20 += 0x20;
};

179
src/eth/regs/eth_mac_25g_us_regs.sv Normal file
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@@ -0,0 +1,179 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
module eth_mac_25g_us_regs (
input wire clk,
input wire rst,
input wire s_apb_psel,
input wire s_apb_penable,
input wire s_apb_pwrite,
input wire [2:0] s_apb_pprot,
input wire [6:0] s_apb_paddr,
input wire [31:0] s_apb_pwdata,
input wire [3:0] s_apb_pstrb,
output logic s_apb_pready,
output logic [31:0] s_apb_prdata,
output logic s_apb_pslverr,
input eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
logic [6:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
logic cpuif_req_stall_rd;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
logic cpuif_wr_ack;
logic cpuif_wr_err;
// Request
logic is_active;
always_ff @(posedge clk) begin
if(rst) begin
is_active <= '0;
cpuif_req <= '0;
cpuif_req_is_wr <= '0;
cpuif_addr <= '0;
cpuif_wr_data <= '0;
cpuif_wr_biten <= '0;
end else begin
if(~is_active) begin
if(s_apb_psel) begin
is_active <= '1;
cpuif_req <= '1;
cpuif_req_is_wr <= s_apb_pwrite;
cpuif_addr <= {s_apb_paddr[6:2], 2'b0};
cpuif_wr_data <= s_apb_pwdata;
for(int i=0; i<4; i++) begin
cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}};
end
end
end else begin
cpuif_req <= '0;
if(cpuif_rd_ack || cpuif_wr_ack) begin
is_active <= '0;
end
end
end
end
// Response
assign s_apb_pready = cpuif_rd_ack | cpuif_wr_ack;
assign s_apb_prdata = cpuif_rd_data;
assign s_apb_pslverr = cpuif_rd_err | cpuif_wr_err;
logic cpuif_req_masked;
// Read & write latencies are balanced. Stalls not required
assign cpuif_req_stall_rd = '0;
assign cpuif_req_stall_wr = '0;
assign cpuif_req_masked = cpuif_req
& !(!cpuif_req_is_wr & cpuif_req_stall_rd)
& !(cpuif_req_is_wr & cpuif_req_stall_wr);
//--------------------------------------------------------------------------
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
struct {
logic xcvr_gtpowergood_out;
logic xcvr_qpll0lock_out;
logic xcvr_qpll1lock_out;
} common;
struct {
logic rx_block_lock;
logic rx_status;
} lanes[2];
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_err;
logic decoded_req;
logic decoded_req_is_wr;
logic [31:0] decoded_wr_data;
logic [31:0] decoded_wr_biten;
always_comb begin
automatic logic is_valid_addr;
automatic logic is_invalid_rw;
is_valid_addr = '1; // No error checking on valid address access
is_invalid_rw = '0;
decoded_reg_strb.common.xcvr_gtpowergood_out = cpuif_req_masked & (cpuif_addr == 7'h0) & !cpuif_req_is_wr;
decoded_reg_strb.common.xcvr_qpll0lock_out = cpuif_req_masked & (cpuif_addr == 7'h4) & !cpuif_req_is_wr;
decoded_reg_strb.common.xcvr_qpll1lock_out = cpuif_req_masked & (cpuif_addr == 7'h8) & !cpuif_req_is_wr;
for(int i0=0; i0<2; i0++) begin
decoded_reg_strb.lanes[i0].rx_block_lock = cpuif_req_masked & (cpuif_addr == 7'h20 + (7)'(i0) * 7'h20) & !cpuif_req_is_wr;
decoded_reg_strb.lanes[i0].rx_status = cpuif_req_masked & (cpuif_addr == 7'h24 + (7)'(i0) * 7'h20) & !cpuif_req_is_wr;
end
decoded_err = (~is_valid_addr | is_invalid_rw) & decoded_req;
end
// Pass down signals to next stage
assign decoded_req = cpuif_req_masked;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
//--------------------------------------------------------------------------
// Field logic
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Write response
//--------------------------------------------------------------------------
assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
// Writes are always granted with no error response
assign cpuif_wr_err = '0;
//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------
logic readback_err;
logic readback_done;
logic [31:0] readback_data;
// Assign readback values to a flattened array
logic [31:0] readback_array[7];
assign readback_array[0][0:0] = (decoded_reg_strb.common.xcvr_gtpowergood_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next : '0;
assign readback_array[0][31:1] = '0;
assign readback_array[1][0:0] = (decoded_reg_strb.common.xcvr_qpll0lock_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next : '0;
assign readback_array[1][31:1] = '0;
assign readback_array[2][0:0] = (decoded_reg_strb.common.xcvr_qpll1lock_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next : '0;
assign readback_array[2][31:1] = '0;
for(genvar i0=0; i0<2; i0++) begin
assign readback_array[i0 * 2 + 3][0:0] = (decoded_reg_strb.lanes[i0].rx_block_lock && !decoded_req_is_wr) ? hwif_in.lanes[i0].rx_block_lock.rx_block_lock.next : '0;
assign readback_array[i0 * 2 + 3][31:1] = '0;
assign readback_array[i0 * 2 + 4][0:0] = (decoded_reg_strb.lanes[i0].rx_status && !decoded_req_is_wr) ? hwif_in.lanes[i0].rx_status.rx_status.next : '0;
assign readback_array[i0 * 2 + 4][31:1] = '0;
end
// Reduce the array
always_comb begin
automatic logic [31:0] readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr;
readback_err = '0;
readback_data_var = '0;
for(int i=0; i<7; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
assign cpuif_rd_ack = readback_done;
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;
endmodule

65
src/eth/regs/eth_mac_25g_us_regs_pkg.sv Normal file
View File

@@ -0,0 +1,65 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
package eth_mac_25g_us_regs_pkg;
localparam ETH_MAC_25G_US_REGS_DATA_WIDTH = 32;
localparam ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH = 7;
localparam ETH_MAC_25G_US_REGS_SIZE = 'h60;
typedef struct {
logic next;
} eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__xcvr_gtpowergood_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__xcvr_gtpowergood_out__in_t xcvr_gtpowergood_out;
} eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__xcvr_qpll0lock_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__xcvr_qpll0lock_out__in_t xcvr_qpll0lock_out;
} eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__xcvr_qpll1lock_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__xcvr_qpll1lock_out__in_t xcvr_qpll1lock_out;
} eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__in_t xcvr_gtpowergood_out;
eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__in_t xcvr_qpll0lock_out;
eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__in_t xcvr_qpll1lock_out;
} eth_mac_25g_us_regs__common__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__lane__rx_block_lock__rx_block_lock__in_t;
typedef struct {
eth_mac_25g_us_regs__lane__rx_block_lock__rx_block_lock__in_t rx_block_lock;
} eth_mac_25g_us_regs__lane__rx_block_lock__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__lane__rx_status__rx_status__in_t;
typedef struct {
eth_mac_25g_us_regs__lane__rx_status__rx_status__in_t rx_status;
} eth_mac_25g_us_regs__lane__rx_status__in_t;
typedef struct {
eth_mac_25g_us_regs__lane__rx_block_lock__in_t rx_block_lock;
eth_mac_25g_us_regs__lane__rx_status__in_t rx_status;
} eth_mac_25g_us_regs__lane__in_t;
typedef struct {
eth_mac_25g_us_regs__common__in_t common;
eth_mac_25g_us_regs__lane__in_t lanes[2];
} eth_mac_25g_us_regs__in_t;
endpackage

6
src/eth/sources.list Normal file
View File

@@ -0,0 +1,6 @@
regs/eth_dma_wrapper_regs_pkg.sv
regs/eth_dma_wrapper_regs.sv
regs/eth_mac_25g_us_regs_pkg.sv
regs/eth_mac_25g_us_regs.sv
eth_dma_wrapper.sv

20
src/pcie_dma_wrapper.sv → src/pcie/pcie_dma_wrapper.sv
View File

@@ -5,6 +5,9 @@ module pcie_dma_wrapper (
taxi_axis_if.src m_axis_rq,
taxi_axis_if.snk s_axis_rc,
taxi_dma_ram_if.wr_mst wr_dma_mst,
taxi_dma_ram_if.rd_mst rd_dma_mst,
taxi_apb_if.slv s_apb
);
@@ -18,9 +21,6 @@ logic seq_num_valid_1;
taxi_dma_desc_if #(.DST_ADDR_W(16)) rd_desc();
taxi_dma_desc_if #(.SRC_ADDR_W(16)) wr_desc();
// the dma just reads and writes from the same memory
taxi_dma_ram_if #(.SEGS(4)) dma_ram_if();
pcie_dma_regs_pkg::pcie_dma_regs__in_t hwif_in;
pcie_dma_regs_pkg::pcie_dma_regs__out_t hwif_out;
@@ -43,16 +43,6 @@ pcie_dma_regs u_pcie_dma_regs(
.hwif_out (hwif_out)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_psdpram (
.clk (clk),
.rst (rst),
.dma_ram_wr (dma_ram_if),
.dma_ram_rd (dma_ram_if)
);
logic [7:0] read_tag;
logic [7:0] write_tag;
@@ -131,8 +121,8 @@ taxi_dma_if_pcie_us #(
.wr_desc_req (wr_desc),
.wr_desc_sts (wr_desc),
.dma_ram_wr (dma_ram_if),
.dma_ram_rd (dma_ram_if),
.dma_ram_wr (wr_dma_mst),
.dma_ram_rd (rd_dma_mst),
.read_enable ('1),
.write_enable ('1),

181
src/pcie/pcie_top.sv Normal file
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@@ -0,0 +1,181 @@
module pcie_top(
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [7:0] pci_exp_txp,
output wire [7:0] pci_exp_txn,
input wire pcie_mgt_refclk_p,
input wire pcie_mgt_refclk_n,
input wire pcie_reset_n,
output wire user_lnk_up,
output wire phy_rdy_out,
output wire o_clk_250,
output wire o_rst_250,
taxi_dma_ram_if.wr_slv dma_ram_eth_wr_if,
taxi_dma_ram_if.rd_slv dma_ram_eth_rd_if,
taxi_axil_if.rd_mst m_axil_rd,
taxi_axil_if.wr_mst m_axil_wr,
taxi_apb_if.slv s_apb
);
logic clk_pcie_gt;
logic clk_pcie;
logic rst_pcie;
logic clk_250;
logic rst_250;
assign o_clk_250 = clk_250;
assign o_rst_250 = rst_250;
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(62), .KEEP_W(8)) s_axis_rq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) pcie_dma_apb();
`ifndef SIM
IBUFDS_GTE4 m_ibufds (
.CEB('0),
.I(pcie_mgt_refclk_p),
.IB(pcie_mgt_refclk_n),
.O(clk_pcie_gt),
.ODIV2(clk_pcie)
);
`endif
pcie_top_regs u_pcie_top_regs (
.s_apb (s_apb),
.m_apb_pcie_dma_regs(pcie_dma_apb)
);
taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
.clk (clk_250),
.rst (rst_250),
.s_axis_cq (m_axis_cq),
.m_axis_cc (s_axis_cc),
.m_axil_wr (m_axil_wr),
.m_axil_rd (m_axil_rd),
.completer_id ('0),
.completer_id_en ('0),
.stat_err_cor (),
.stat_err_uncor ()
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_tx_psdpram (
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_pcie_wr_if),
.dma_ram_rd (dma_ram_eth_rd_if)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_rx_psdpram(
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_eth_wr_if),
.dma_ram_rd (dma_ram_pcie_rd_if)
);
pcie_dma_wrapper u_pcie_dma_wrapper (
.clk (clk_250),
.rst (rst_250),
.m_axis_rq (s_axis_rq),
.s_axis_rc (m_axis_rc),
.wr_dma_mst (dma_ram_pcie_wr_if),
.rd_dma_mst (dma_ram_pcie_rd_if),
.s_apb (pcie_dma_apb)
);
`ifndef SIM
pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
.pci_exp_txn(pci_exp_txn),
.pci_exp_txp(pci_exp_txp),
.pci_exp_rxn(pci_exp_rxn),
.pci_exp_rxp(pci_exp_rxp),
.user_clk(clk_250),
.user_reset(rst_250),
.user_lnk_up(user_lnk_up),
.s_axis_rq_tdata(s_axis_rq.tdata),
.s_axis_rq_tkeep(s_axis_rq.tkeep),
.s_axis_rq_tlast(s_axis_rq.tlast),
.s_axis_rq_tready(s_axis_rq.tready),
.s_axis_rq_tuser(s_axis_rq.tuser),
.s_axis_rq_tvalid(s_axis_rq.tvalid),
.m_axis_rc_tdata(m_axis_rc.tdata),
.m_axis_rc_tkeep(m_axis_rc.tkeep),
.m_axis_rc_tlast(m_axis_rc.tlast),
.m_axis_rc_tready(m_axis_rc.tready),
.m_axis_rc_tuser(m_axis_rc.tuser),
.m_axis_rc_tvalid(m_axis_rc.tvalid),
.m_axis_cq_tdata(m_axis_cq.tdata),
.m_axis_cq_tkeep(m_axis_cq.tkeep),
.m_axis_cq_tlast(m_axis_cq.tlast),
.m_axis_cq_tready(m_axis_cq.tready),
.m_axis_cq_tuser(m_axis_cq.tuser),
.m_axis_cq_tvalid(m_axis_cq.tvalid),
.s_axis_cc_tdata(s_axis_cc.tdata),
.s_axis_cc_tkeep(s_axis_cc.tkeep),
.s_axis_cc_tlast(s_axis_cc.tlast),
.s_axis_cc_tready(s_axis_cc.tready),
.s_axis_cc_tuser(s_axis_cc.tuser),
.s_axis_cc_tvalid(s_axis_cc.tvalid),
.cfg_interrupt_int('0),
.cfg_interrupt_pending(),
.cfg_interrupt_sent('0),
.cfg_interrupt_msi_enable(),
.cfg_interrupt_msi_mmenable(),
.cfg_interrupt_msi_mask_update(),
.cfg_interrupt_msi_data(),
.cfg_interrupt_msi_select('0),
.cfg_interrupt_msi_int('0),
.cfg_interrupt_msi_pending_status('0),
.cfg_interrupt_msi_pending_status_data_enable('0),
.cfg_interrupt_msi_pending_status_function_num('0),
.cfg_interrupt_msi_sent(),
.cfg_interrupt_msi_fail(),
.cfg_interrupt_msi_attr('0),
.cfg_interrupt_msi_tph_present('0),
.cfg_interrupt_msi_tph_type('0),
.cfg_interrupt_msi_tph_st_tag('0),
.cfg_interrupt_msi_function_number('0),
.sys_clk(clk_pcie),
.sys_clk_gt(clk_pcie_gt),
.sys_reset(pcie_reset_n),
.phy_rdy_out(phy_rdy_out)
);
`endif
endmodule

2
src/pcie/regs/compile_regs.sh Executable file
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@@ -0,0 +1,2 @@
peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif taxi-apb

0
src/regs/pcie_dma_regs.rdl → src/pcie/regs/pcie_dma_regs.rdl
View File

0
src/regs/pcie_dma_regs.sv → src/pcie/regs/pcie_dma_regs.sv
View File

0
src/regs/pcie_dma_regs_pkg.sv → src/pcie/regs/pcie_dma_regs_pkg.sv
View File

6
src/pcie/regs/pcie_top_regs.rdl Normal file
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@@ -0,0 +1,6 @@
addrmap pcie_top_regs {
name = "";
desc = "";
external pcie_dma_regs pcie_dma_regs;
};

147
src/pcie/regs/pcie_top_regs.sv Normal file
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@@ -0,0 +1,147 @@
//==========================================================
// Module: pcie_top_regs
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
module pcie_top_regs (
taxi_apb_if.slv s_apb,
taxi_apb_if.mst m_apb_pcie_dma_regs
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_wr_en;
logic cpuif_rd_en;
logic [5:0] cpuif_wr_addr;
logic [5:0] cpuif_rd_addr;
logic cpuif_wr_ack;
logic cpuif_wr_err;
logic [31:0] cpuif_wr_data;
logic [3:0] cpuif_wr_byte_en;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
//--------------------------------------------------------------------------
// Child instance signals
//--------------------------------------------------------------------------
typedef struct {
logic pcie_dma_regs;
logic cpuif_err;
} cpuif_sel_t;
cpuif_sel_t cpuif_wr_sel;
cpuif_sel_t cpuif_rd_sel;
//--------------------------------------------------------------------------
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
`ifndef SYNTHESIS
initial begin
assert_bad_addr_width: assert($bits(s_apb.paddr) >= pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)
else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH);
assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH);
end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
`endif
assign cpuif_req = s_apb.psel;
assign cpuif_wr_en = s_apb.pwrite;
assign cpuif_rd_en = !s_apb.pwrite;
assign cpuif_wr_addr = s_apb.paddr;
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.pstrb;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;
assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.penable = s_apb.penable;
assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Intermediate signals for interface array fanin
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
cpuif_rd_ack = '0;
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
end
end
//--------------------------------------------------------------------------
// Write Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all write select signals to 0
cpuif_wr_sel = '{default: '0};
if (cpuif_req && cpuif_wr_en) begin
// A write request is pending
if ((cpuif_wr_addr < (6'h38))) begin
cpuif_wr_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_wr_sel.cpuif_err = 1'b1;
end
end else begin
// No write request, all select signals remain 0
end
end
//--------------------------------------------------------------------------
// Read Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all read select signals to 0
cpuif_rd_sel = '{default: '0};
if (cpuif_req && cpuif_rd_en) begin
// A read request is pending
if ((cpuif_rd_addr < (6'h38))) begin
cpuif_rd_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_rd_sel.cpuif_err = 1'b1;
end
end else begin
// No read request, all select signals remain 0
end
end
endmodule

18
src/pcie/regs/pcie_top_regs_pkg.sv Normal file
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@@ -0,0 +1,18 @@
//==========================================================
// Package: pcie_top_regs_pkg
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
package pcie_top_regs_pkg;
localparam PCIE_TOP_REGS_DATA_WIDTH = 32;
localparam PCIE_TOP_REGS_MIN_ADDR_WIDTH = 6;
localparam PCIE_TOP_REGS_SIZE = 'h38;
localparam PCIE_TOP_REGS_PCIE_DMA_REGS_ADDR_WIDTH = 6;
endpackage

4
src/pcie/regs/verilator.vlt Normal file
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@@ -0,0 +1,4 @@
`verilator_config
lint_off -rule MULTIDRIVEN -file "**/regs/*"
lint_off -file "**/regs/*"

9
src/pcie/sources.list Normal file
View File

@@ -0,0 +1,9 @@
regs/verilator.vlt
regs/pcie_dma_regs_pkg.sv
regs/pcie_dma_regs.sv
regs/pcie_top_regs_pkg.sv
regs/pcie_top_regs.sv
pcie_dma_wrapper.sv
pcie_top.sv

6
src/regs/alibaba_pcie_top.rdl Normal file
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@@ -0,0 +1,6 @@
addrmap alibaba_pcie_top_regs {
name = "Alibaba PCIe Top";
external pcie_top_regs pcie_top_regs;
external eth_dma_wrapper_regs eth_dma_wrapper_regs;
};

190
src/regs/alibaba_pcie_top_regs.h Normal file
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@@ -0,0 +1,190 @@
// Generated by PeakRDL-cheader - A free and open-source header generator
// https://github.com/SystemRDL/PeakRDL-cheader
#ifndef ALIBABA_PCIE_TOP_REGS_H
#define ALIBABA_PCIE_TOP_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <assert.h>
// Reg - pcie_dma_regs::dma_rd::src_addr_low
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_rd::src_addr_high
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_rd::dst_addr
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bm 0xffff
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bw 16
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_rd::length
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bm 0xffff
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bp 0
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bw 16
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_reset 0x0
// Reg - pcie_dma_regs::dma_rd::trigger
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bm 0x1
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bp 0
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bw 1
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_reset 0x0
// Reg - pcie_dma_regs::dma_rd::done
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bm 0x1
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bp 0
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bw 1
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_reset 0x0
// Regfile - pcie_dma_regs::dma_rd
typedef struct __attribute__ ((__packed__)) {
uint32_t src_addr_low;
uint32_t src_addr_high;
uint32_t dst_addr;
uint32_t length;
uint32_t trigger;
uint32_t done;
} pcie_dma_regs__dma_rd_t;
// Reg - pcie_dma_regs::dma_wr::dst_addr_low
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_wr::dst_addr_high
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_wr::src_addr
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bm 0xffff
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bw 16
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_wr::length
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bm 0xffff
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bp 0
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bw 16
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_reset 0x0
// Reg - pcie_dma_regs::dma_wr::trigger
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bm 0x1
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bp 0
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bw 1
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_reset 0x0
// Reg - pcie_dma_regs::dma_wr::done
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bm 0x1
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bp 0
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bw 1
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_reset 0x0
// Regfile - pcie_dma_regs::dma_wr
typedef struct __attribute__ ((__packed__)) {
uint32_t dst_addr_low;
uint32_t dst_addr_high;
uint32_t src_addr;
uint32_t length;
uint32_t trigger;
uint32_t done;
} pcie_dma_regs__dma_wr_t;
// Addrmap - pcie_dma_regs
typedef struct __attribute__ ((__packed__)) {
pcie_dma_regs__dma_rd_t dma_rd;
uint8_t RESERVED_18_1f[0x8];
pcie_dma_regs__dma_wr_t dma_wr;
} pcie_dma_regs_t;
// Addrmap - pcie_top_regs
typedef struct __attribute__ ((__packed__)) {
pcie_dma_regs_t pcie_dma_regs;
} pcie_top_regs_t;
// Reg - eth_mac_25g_us_regs::common::xcvr_gtpowergood_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_reset 0x0
// Reg - eth_mac_25g_us_regs::common::xcvr_qpll0lock_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_reset 0x0
// Reg - eth_mac_25g_us_regs::common::xcvr_qpll1lock_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_reset 0x0
// Regfile - eth_mac_25g_us_regs::common
typedef struct __attribute__ ((__packed__)) {
uint32_t xcvr_gtpowergood_out;
uint32_t xcvr_qpll0lock_out;
uint32_t xcvr_qpll1lock_out;
} eth_mac_25g_us_regs__common_t;
// Reg - eth_mac_25g_us_regs::lane::rx_block_lock
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bm 0x1
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bp 0
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bw 1
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_reset 0x0
// Reg - eth_mac_25g_us_regs::lane::rx_status
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bm 0x1
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bp 0
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bw 1
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_reset 0x0
// Regfile - eth_mac_25g_us_regs::lane
typedef struct __attribute__ ((__packed__)) {
uint32_t rx_block_lock;
uint32_t rx_status;
uint8_t RESERVED_8_1f[0x18];
} eth_mac_25g_us_regs__lane__stride20_t;
// Addrmap - eth_mac_25g_us_regs
typedef struct __attribute__ ((__packed__)) {
eth_mac_25g_us_regs__common_t common;
uint8_t RESERVED_c_1f[0x14];
eth_mac_25g_us_regs__lane__stride20_t lanes[2];
} eth_mac_25g_us_regs_t;
// Addrmap - eth_dma_wrapper_regs
typedef struct __attribute__ ((__packed__)) {
eth_mac_25g_us_regs_t eth_mac_25g_us_regs;
uint8_t RESERVED_60_7f[0x20];
pcie_dma_regs_t pcie_dma_regs;
} eth_dma_wrapper_regs_t;
// Addrmap - alibaba_pcie_top_regs
typedef struct __attribute__ ((__packed__)) {
pcie_top_regs_t pcie_top_regs;
uint8_t RESERVED_38_ff[0xc8];
eth_dma_wrapper_regs_t eth_dma_wrapper_regs;
} alibaba_pcie_top_regs_t;
static_assert(sizeof(alibaba_pcie_top_regs_t) == 0x1b8, "Packing error");
#ifdef __cplusplus
}
#endif
#endif /* ALIBABA_PCIE_TOP_REGS_H */

169
src/regs/alibaba_pcie_top_regs.sv Normal file
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@@ -0,0 +1,169 @@
//==========================================================
// Module: alibaba_pcie_top_regs
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
module alibaba_pcie_top_regs (
taxi_apb_if.slv s_apb,
taxi_apb_if.mst m_apb_pcie_top_regs,
taxi_apb_if.mst m_apb_eth_dma_wrapper_regs
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_wr_en;
logic cpuif_rd_en;
logic [8:0] cpuif_wr_addr;
logic [8:0] cpuif_rd_addr;
logic cpuif_wr_ack;
logic cpuif_wr_err;
logic [31:0] cpuif_wr_data;
logic [3:0] cpuif_wr_byte_en;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
//--------------------------------------------------------------------------
// Child instance signals
//--------------------------------------------------------------------------
typedef struct {
logic pcie_top_regs;
logic eth_dma_wrapper_regs;
logic cpuif_err;
} cpuif_sel_t;
cpuif_sel_t cpuif_wr_sel;
cpuif_sel_t cpuif_rd_sel;
//--------------------------------------------------------------------------
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
`ifndef SYNTHESIS
initial begin
assert_bad_addr_width: assert($bits(s_apb.paddr) >= alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)
else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH);
assert_bad_data_width: assert($bits(s_apb.pwdata) == alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH);
end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
`endif
assign cpuif_req = s_apb.psel;
assign cpuif_wr_en = s_apb.pwrite;
assign cpuif_rd_en = !s_apb.pwrite;
assign cpuif_wr_addr = s_apb.paddr;
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.pstrb;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;
assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_top_regs.psel = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
assign m_apb_pcie_top_regs.penable = s_apb.penable;
assign m_apb_pcie_top_regs.pwrite = cpuif_wr_sel.pcie_top_regs;
assign m_apb_pcie_top_regs.paddr = s_apb.paddr;
assign m_apb_pcie_top_regs.pprot = s_apb.pprot;
assign m_apb_pcie_top_regs.pwdata = cpuif_wr_data;
assign m_apb_pcie_top_regs.pstrb = cpuif_wr_byte_en;
assign m_apb_eth_dma_wrapper_regs.psel = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs.penable = s_apb.penable;
assign m_apb_eth_dma_wrapper_regs.pwrite = cpuif_wr_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs.paddr = s_apb.paddr;
assign m_apb_eth_dma_wrapper_regs.pprot = s_apb.pprot;
assign m_apb_eth_dma_wrapper_regs.pwdata = cpuif_wr_data;
assign m_apb_eth_dma_wrapper_regs.pstrb = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Intermediate signals for interface array fanin
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
cpuif_rd_ack = '0;
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin
cpuif_rd_ack = m_apb_pcie_top_regs.pready;
cpuif_rd_err = m_apb_pcie_top_regs.pslverr;
end
if (cpuif_rd_sel.pcie_top_regs) begin
cpuif_rd_data = m_apb_pcie_top_regs.prdata;
end
if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin
cpuif_rd_ack = m_apb_eth_dma_wrapper_regs.pready;
cpuif_rd_err = m_apb_eth_dma_wrapper_regs.pslverr;
end
if (cpuif_rd_sel.eth_dma_wrapper_regs) begin
cpuif_rd_data = m_apb_eth_dma_wrapper_regs.prdata;
end
end
//--------------------------------------------------------------------------
// Write Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all write select signals to 0
cpuif_wr_sel = '{default: '0};
if (cpuif_req && cpuif_wr_en) begin
// A write request is pending
if ((cpuif_wr_addr < (9'h38))) begin
cpuif_wr_sel.pcie_top_regs = 1'b1;
end
else if ((cpuif_wr_addr >= (9'h100)) && (cpuif_wr_addr < (9'h1b8))) begin
cpuif_wr_sel.eth_dma_wrapper_regs = 1'b1;
end
else begin
cpuif_wr_sel.cpuif_err = 1'b1;
end
end else begin
// No write request, all select signals remain 0
end
end
//--------------------------------------------------------------------------
// Read Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all read select signals to 0
cpuif_rd_sel = '{default: '0};
if (cpuif_req && cpuif_rd_en) begin
// A read request is pending
if ((cpuif_rd_addr < (9'h38))) begin
cpuif_rd_sel.pcie_top_regs = 1'b1;
end
else if ((cpuif_rd_addr >= (9'h100)) && (cpuif_rd_addr < (9'h1b8))) begin
cpuif_rd_sel.eth_dma_wrapper_regs = 1'b1;
end
else begin
cpuif_rd_sel.cpuif_err = 1'b1;
end
end else begin
// No read request, all select signals remain 0
end
end
endmodule

19
src/regs/alibaba_pcie_top_regs_pkg.sv Normal file
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@@ -0,0 +1,19 @@
//==========================================================
// Package: alibaba_pcie_top_regs_pkg
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
package alibaba_pcie_top_regs_pkg;
localparam ALIBABA_PCIE_TOP_REGS_DATA_WIDTH = 32;
localparam ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH = 9;
localparam ALIBABA_PCIE_TOP_REGS_SIZE = 'h1b8;
localparam ALIBABA_PCIE_TOP_REGS_PCIE_TOP_REGS_ADDR_WIDTH = 6;
localparam ALIBABA_PCIE_TOP_REGS_ETH_DMA_WRAPPER_REGS_ADDR_WIDTH = 8;
endpackage

4
src/regs/compile_regs.sh
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@@ -1 +1,3 @@
peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl"
peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb

2
sub/taxi

Submodule sub/taxi updated: c6eac348f6...2391e4f366

24
sub/taxi_sources.list
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@@ -1,3 +1,8 @@
taxi/src/apb/rtl/taxi_apb_adapter.sv
taxi/src/apb/rtl/taxi_apb_dp_ram.sv
taxi/src/apb/rtl/taxi_apb_if.sv
taxi/src/apb/rtl/taxi_apb_interconnect.sv
taxi/src/apb/rtl/taxi_apb_ram.sv
taxi/src/axi/rtl/taxi_axi_if.sv
taxi/src/axi/rtl/taxi_axil_register_wr.sv
taxi/src/axi/rtl/taxi_axi_axil_adapter.sv
@@ -59,6 +64,7 @@ taxi/src/axis/rtl/taxi_axis_arb_mux.f
taxi/src/axis/rtl/taxi_axis_null_src.sv
#taxi/src/axis/rtl/taxi_axis_switch.sv
taxi/src/axis/rtl/taxi_axis_fifo.sv
taxi/src/axis/syn/vivado/taxi_axis_async_fifo.tcl
taxi/src/pcie/rtl/taxi_pcie_us_axil_master.sv
taxi/src/pcie/rtl/taxi_pcie_tlp_if.sv
taxi/src/pcie/rtl/taxi_pcie_axil_master.sv
@@ -82,9 +88,6 @@ taxi/src/dma/rtl/taxi_dma_if_pcie_us_wr.sv
taxi/src/dma/rtl/taxi_dma_psdpram.sv
taxi/src/dma/rtl/taxi_dma_psdpram_async.sv
taxi/src/dma/rtl/taxi_dma_ram_if.sv
taxi/src/apb/rtl/taxi_apb_dp_ram.sv
taxi/src/apb/rtl/taxi_apb_if.sv
taxi/src/apb/rtl/taxi_apb_ram.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_rgmii.sv
taxi/src/eth/rtl/taxi_axis_gmii_rx.sv
@@ -128,8 +131,23 @@ taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv
taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv
taxi/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv
taxi/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv
#taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_apb.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv
taxi/src/eth/rtl/taxi_axis_xgmii_tx_32.sv
taxi/src/eth/rtl/taxi_eth_mac_stats.sv
taxi/src/eth/rtl/taxi_rgmii_phy_if.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_tx.sv
taxi/src/lfsr/rtl/taxi_lfsr_crc.sv
taxi/src/lfsr/rtl/taxi_lfsr_descramble.sv
taxi/src/lfsr/rtl/taxi_lfsr_prbs_check.sv
taxi/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv
taxi/src/lfsr/rtl/taxi_lfsr_scramble.sv
taxi/src/lfsr/rtl/taxi_lfsr.sv
taxi/src/sync/rtl/taxi_sync_reset.sv
taxi/src/sync/rtl/taxi_sync_signal.sv
taxi/src/sync/syn/vivado/taxi_sync_reset.tcl
taxi/src/sync/syn/vivado/taxi_sync_signal.tcl
taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv
taxi/src/hip/rtl/us/taxi_mmcm_frac.sv