bslathi19/fpga-sim
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Byron Lathi 1addf6e52f Merge branch 'filter_verilog' into 'master' 
Filter out only verilog sources (and verilator lint files)

See merge request bslathi19/fpga-sim!4
2025-03-30 04:37:30 +00:00
src/fpga_sim
Filter out only verilog sources (and verilator lint files)
2025-03-29 19:39:35 -07:00
.gitignore
Initial commit
2024-11-29 22:31:03 -08:00
.gitlab-ci.yml
Initial commit
2024-11-29 22:31:03 -08:00
init_env.sh
Initial commit
2024-11-29 22:31:03 -08:00
LICENSE.txt
Initial commit
2024-11-29 22:31:03 -08:00
pyproject.toml
Filter out only verilog sources (and verilator lint files)
2025-03-29 19:39:35 -07:00
README.md
Initial commit
2024-11-29 22:31:03 -08:00
requirements.txt
Experimental/incdirs
2025-03-21 05:45:28 +00:00

README.md

FPGA Sim

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Description
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Readme 107 KiB
Languages
Python 98%
Shell 2%