Upon receiving an interrupt, the corresponding bit in the interrupt
status register will be set and an IRQ will be raised for the CPU. The
cpu can then respond to the interrupt and clear the interrupt by writing
back to the interrupt status register.
The write task will transmit a single byte, the puts task will transmit
a string of length n. These do not do any verification, you still have
to look at the output.
Added new signal tx_flag, which indicates whether the transmitter is
ready for new data.
Added status register, which when read will return the tx_flag bit, as
well as others that can be implemented.
Added new state IDLE, which resets the TX flag and allows new data to be
written.
Added code to allow for different baud rates, though it is still fixed
currently.
This also increases the number of registers to 4, one more for the high
pair of displays, and a final one for a mask register which has not been
implemented yet.
