Alex Forencich
|
a16a667f81
|
lss: Add I2C init module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:20:21 -07:00 |
|
Alex Forencich
|
d4089096ae
|
example: Add example design for HTG-9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:19:58 -07:00 |
|
Alex Forencich
|
467b044e88
|
lss: Add missing file list file handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 15:15:29 -07:00 |
|
Alex Forencich
|
89f60f26ff
|
lss: Add some interface configuration checks to I2C modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 14:40:56 -07:00 |
|
Alex Forencich
|
8017534c45
|
lss: Rename I2C data ports to reduce ambiguity
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 14:40:33 -07:00 |
|
Alex Forencich
|
4620370035
|
lss: Add I2C slave AXI lite master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 00:44:14 -07:00 |
|
Alex Forencich
|
37825a02f4
|
lss: Add I2C slave module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 00:22:11 -07:00 |
|
Alex Forencich
|
8bcd7ca037
|
axis: Expand size range for concatenator module tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-31 14:13:13 -07:00 |
|
Alex Forencich
|
933899887a
|
axis: Add AXI stream switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-31 11:47:49 -07:00 |
|
Alex Forencich
|
dd8b2a89ed
|
axis: Remove unnecessary idle cycles in taxi_axis_concat
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 22:03:16 -07:00 |
|
Alex Forencich
|
bd0b0cd75a
|
Update documentation URL
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 19:12:45 -07:00 |
|
Alex Forencich
|
d10e3cf5c0
|
axis: Add AXI stream demultiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 19:10:48 -07:00 |
|
Alex Forencich
|
b266aa2949
|
axis: Add AXI stream concatenator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 18:57:11 -07:00 |
|
Alex Forencich
|
059c7cd5ce
|
axis: Minor cleanup in taxi_axis_mux
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-29 09:43:11 -07:00 |
|
Alex Forencich
|
75a8750679
|
axis: Minor cleanup in taxi_axis_arb_mux
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-29 09:40:03 -07:00 |
|
Alex Forencich
|
2065151c01
|
eth: Update 10G-only example designs to use 32-bit MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 23:19:30 -07:00 |
|
Alex Forencich
|
7031a3f0b1
|
eth: Add 32-bit mode tests for UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 22:19:55 -07:00 |
|
Alex Forencich
|
5b0cae2aac
|
eth: Add 32-bit support to combined MAC+PCS module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:37:34 -07:00 |
|
Alex Forencich
|
7b1ae24d95
|
eth: Report framing and bad block errors in 32-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:34:42 -07:00 |
|
Alex Forencich
|
fd521a1511
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:50 -07:00 |
|
Alex Forencich
|
295dc2dd23
|
eth: Add 32-bit AXI stream BASE-R RX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:09 -07:00 |
|
Alex Forencich
|
ebb8bf0bd4
|
eth: Add 32-bit AXI stream BASE-R TX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:14:30 -07:00 |
|
Alex Forencich
|
6f5adb1b41
|
eth: Reset pack_seq even if the header is not marked as valid
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 16:32:48 -07:00 |
|
Alex Forencich
|
e8cea4c860
|
eth: Use for loop to reduce duplication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 11:50:29 -07:00 |
|
Alex Forencich
|
facdc5fe68
|
eth: Remove extraneous constants
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-16 16:01:12 -07:00 |
|
Alex Forencich
|
17e48c5f51
|
eth: Support 32-bit mode in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:16:58 -07:00 |
|
Alex Forencich
|
6407b4c7f0
|
eth: Support 32-bit sync gearbox in 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:11:26 -07:00 |
|
Alex Forencich
|
ab09ceb891
|
eth: Support 32 bit mode in BASE-R PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:00:14 -07:00 |
|
Alex Forencich
|
e6b5cd6ecd
|
eth: Support 32 bit mode in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:56:03 -07:00 |
|
Alex Forencich
|
70c0e3d52a
|
eth: Fix RX BER monitor when gearbox is enabled
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:54:01 -07:00 |
|
Alex Forencich
|
2e1619a045
|
eth: Connect and tie off txsequence
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 01:20:23 -07:00 |
|
Alex Forencich
|
cc8ec558bf
|
eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-14 22:54:09 -07:00 |
|
Alex Forencich
|
e993a6cfbf
|
eth: Cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 19:38:06 -07:00 |
|
Alex Forencich
|
65eef8b5e8
|
eth: Parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 19:28:21 -07:00 |
|
Alex Forencich
|
eae4d67367
|
eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 17:57:57 -07:00 |
|
Alex Forencich
|
f9041cd9d2
|
eth: Fix multidriven net
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:51:07 -07:00 |
|
Alex Forencich
|
280e5129b8
|
example: Build all MAC variants for ZCU106
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:48:22 -07:00 |
|
Alex Forencich
|
3349561810
|
eth: Remove extraneous defaults
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:45:00 -07:00 |
|
Alex Forencich
|
741615f203
|
eth: Fix parameter name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:40:32 -07:00 |
|
Alex Forencich
|
e846e7f0cd
|
eth: Add gearbox support to 64-bit 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:39:55 -07:00 |
|
Alex Forencich
|
28195390a2
|
eth: Add GBX_CNT to taxi_xgmii_baser_enc_64 testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:35:04 -07:00 |
|
Alex Forencich
|
d4acf48e0a
|
eth: Fix gearbox interface in 10G PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:34:44 -07:00 |
|
Alex Forencich
|
0fd4000f69
|
eth: Support both split and combined MAC/PCS in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 14:31:14 -07:00 |
|
Alex Forencich
|
886aa65522
|
eth: Add testbench for taxi_eth_mac_25g_us module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 10:34:43 -07:00 |
|
Alex Forencich
|
98d06954cc
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 10:28:53 -07:00 |
|
Alex Forencich
|
4e66dd0f98
|
eth: Rename gearbox start signals to sync
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-12 15:45:07 -07:00 |
|
Alex Forencich
|
ca3ee2d197
|
eth: Fix PFC/LFC parameters in 25G MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-12 14:56:55 -07:00 |
|
Alex Forencich
|
a146aeaf21
|
lfsr: Merge output state with data when possible
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 18:48:07 -07:00 |
|
Alex Forencich
|
faa914c828
|
lfsr: Merge input state with data when possible
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 18:30:31 -07:00 |
|
Alex Forencich
|
a4ac9e7bb0
|
lfsr: Add PCIe scramlber sequence as a galois-mode PRBS test
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 13:06:51 -07:00 |
|