Alex Forencich
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38ae0c1587
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eth: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 15:18:23 -07:00 |
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Alex Forencich
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9307e0df6c
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pcie: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 15:17:46 -07:00 |
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Alex Forencich
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1e12094f45
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stats: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 14:58:16 -07:00 |
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Alex Forencich
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32ed95893c
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dma: Clean up casts in DMA PSDPRAM model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 14:37:41 -07:00 |
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Alex Forencich
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e42a2dd8b4
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lss: Use cocotb.start_soon instead of cocotb.fork
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 14:36:27 -07:00 |
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Alex Forencich
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6a5faf9ebf
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Cast to int instead of using .integer
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 11:25:34 -07:00 |
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Alex Forencich
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40908b1b92
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Testbench cleanup for cocotb 2.0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 10:59:38 -07:00 |
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Alex Forencich
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884fe1a006
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apb: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-06 16:50:44 -07:00 |
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Alex Forencich
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81a918d223
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apb: Add SV interface for APB
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-06 16:50:38 -07:00 |
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Alex Forencich
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20f14ace97
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-06 07:06:50 -07:00 |
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Alex Forencich
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553dea534e
|
eth/example/HTG_ZRF8: Add example design for HTG-ZRF8-EM and HTG-ZRF8-R2
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-06 07:03:35 -07:00 |
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Alex Forencich
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0d7e0cf590
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eth/example/ZCU111: Clean up RFDC clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-05 07:30:30 -07:00 |
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Alex Forencich
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6c9026bccf
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eth/example/HTG9200: Fix refclock frequency in testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-05 07:15:26 -07:00 |
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Alex Forencich
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2ae5b5fae3
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pcie: Remove TLP_HDR_W parameter from testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-01 22:08:18 -07:00 |
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Alex Forencich
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cdfb1566f5
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:38:06 -07:00 |
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Alex Forencich
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a6db298eeb
|
dma: Add async DMA PSDPRAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-31 21:30:25 -07:00 |
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Alex Forencich
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48da5315fe
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dma: Add DMA PSDPRAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:29:55 -07:00 |
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Alex Forencich
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d57b49b29c
|
dma: Add PSDPRAM simulation model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-31 21:05:20 -07:00 |
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Alex Forencich
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c5fea4d920
|
dma: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:04:44 -07:00 |
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Alex Forencich
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10500e6c6c
|
dma: Add DMA RAM interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:04:22 -07:00 |
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Alex Forencich
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e87e16c299
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axi: Add AXI FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 22:17:53 -07:00 |
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Alex Forencich
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0080125120
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axi: Add AXI to AXI lite adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 21:11:20 -07:00 |
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Alex Forencich
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94a821192c
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axi: Add AXI width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 21:10:08 -07:00 |
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Alex Forencich
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5f6487964e
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axi: Add MAX_BURST_LEN and NARROW_BURST_EN parameters to AXI interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 13:55:33 -07:00 |
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Alex Forencich
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e43d6acbbd
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axi: Add AXI lite to AXI adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 13:40:43 -07:00 |
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Alex Forencich
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c22e659259
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axi: Add AXI lite width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 13:02:27 -07:00 |
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Alex Forencich
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4dd84efd6c
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 18:00:22 -07:00 |
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Alex Forencich
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bf584147a1
|
pcie: Clean up AXI lite interface width handling in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 17:59:56 -07:00 |
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Alex Forencich
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b3441f6408
|
pcie: Rename enable to en in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 17:59:33 -07:00 |
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Alex Forencich
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63c961cab4
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pcie: Fix some corner cases in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 16:50:31 -07:00 |
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Alex Forencich
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b5c9c02b03
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pcie: Add UltraScale PCIe AXI Lite Master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-25 22:39:28 -07:00 |
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Alex Forencich
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06e6f3e1b4
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lss: Optimize delay implementation in I2C master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:30:03 -07:00 |
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Alex Forencich
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c2c4f5316d
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xfcp: Fix width
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:26:25 -07:00 |
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Alex Forencich
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07ae2ba989
|
eth: Add RFDC to ZCU111 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:26:14 -07:00 |
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Alex Forencich
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4c43b68f94
|
eth: Add 6QSFP FMC support to HTG9200 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 16:24:39 -07:00 |
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Alex Forencich
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cf0ec74849
|
eth: HTG9200 example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 06:37:14 -07:00 |
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Alex Forencich
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5e890bc6cd
|
axis: Add AXI stream tie and null source/sink modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 06:33:21 -07:00 |
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Alex Forencich
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a8dbe26f12
|
zircon: tdest not used on TX path after length/checksum computation, which also extracts the tdest value
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-15 13:36:14 -07:00 |
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Alex Forencich
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3a07e3e28c
|
zircon: Improve sideband signal handling in length/checksum computation module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-15 13:34:15 -07:00 |
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Alex Forencich
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d0efd5f24c
|
zircon: Connect tdest
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-14 14:11:55 -07:00 |
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Alex Forencich
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9955b79fcd
|
zircon: Add FIFO configuration parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-13 17:17:34 -07:00 |
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Alex Forencich
|
af8daa89ce
|
zircon: Fix flow control bug in parser
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-13 13:44:49 -07:00 |
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Alex Forencich
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0aad8ef2cc
|
zircon: Fix testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:33:05 -07:00 |
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Alex Forencich
|
e5ce27cc30
|
zircon: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:13:47 -07:00 |
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Alex Forencich
|
67bfb947f4
|
zircon: Add TX buffer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:09:04 -07:00 |
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Alex Forencich
|
18fdf53d5d
|
zircon: Add ingress and egress modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:08:40 -07:00 |
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Alex Forencich
|
48465423fb
|
zircon: Add length and checksum computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:06:12 -07:00 |
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Alex Forencich
|
7c1f2652b6
|
zircon: Add TX deparser module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 14:57:14 -07:00 |
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Alex Forencich
|
babce69bd0
|
zircon: Add RX parser module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 14:49:22 -07:00 |
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Alex Forencich
|
65cb6124c4
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:20:34 -07:00 |
|