Alex Forencich
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79a1438230
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lfsr: Remove debug prints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-11 13:03:10 -07:00 |
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Alex Forencich
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f7315b7675
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lfsr: Clean up LFSR implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-11 00:35:36 -07:00 |
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Alex Forencich
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4e7e39828b
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lfsr: Add tests for PCIe gen 3 scrambler
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-10 23:56:55 -07:00 |
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Alex Forencich
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e36ac879f7
|
lfsr: Add support for non-self-synchronizing scrambler, add tests for PCIe gen 1/2 scrambler
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-10 23:20:42 -07:00 |
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Alex Forencich
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90780aa0b5
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lfsr: Fix alignment
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-10 22:41:31 -07:00 |
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Alex Forencich
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a1e24f2d7f
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lfsr: Add input and output enable parameters to LFSR module to remove dead code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-10 19:08:55 -07:00 |
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Alex Forencich
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16395bd5cd
|
lss: Fix I2C waveforms
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-10 16:45:27 -07:00 |
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Alex Forencich
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3ec52611eb
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ptp: Adjust testbench thresholds
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-30 22:11:36 -07:00 |
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Alex Forencich
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0eec8eb5be
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ci: Update verilator to 5.034
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-30 21:47:36 -07:00 |
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Alex Forencich
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e4762b7a8c
|
eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-30 21:14:54 -07:00 |
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Alex Forencich
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f31ba113d2
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example: Fix KCU105 TX disable pin constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-30 18:54:45 -07:00 |
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Alex Forencich
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aa8f19bf3b
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eth: Reorganize clock enable in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-27 23:56:28 -07:00 |
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Alex Forencich
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9bce7f4165
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eth: Shorten header argument name in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-27 21:27:46 -07:00 |
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Alex Forencich
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8a77ee9fc7
|
eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-21 21:06:45 -07:00 |
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Alex Forencich
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66b53d98a2
|
Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-18 12:25:59 -07:00 |
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Alex Forencich
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8cdae180a1
|
example/Alveo: fix XFCP UART connection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-07 15:19:57 -07:00 |
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Alex Forencich
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add5662098
|
eth: Add RX MAC control frame count to MAC statistics counters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-07 14:48:33 -07:00 |
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Alex Forencich
|
7bfc62d0d2
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example: Add example design for BittWare XUP-P3R/XUSP3S
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-02 00:08:20 -07:00 |
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Alex Forencich
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e49adb2488
|
pcie: Add PCIe AXI lite master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-29 22:27:32 -07:00 |
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Alex Forencich
|
df87e87e2d
|
pcie: Add PCIe AXI lite master (minimal) module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-29 22:26:19 -07:00 |
|
Alex Forencich
|
093373a2b3
|
pcie: Add generic PCIe interface model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-29 22:25:33 -07:00 |
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Alex Forencich
|
98aeac03b1
|
pcie: Add PCIe TLP interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-29 20:56:23 -07:00 |
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Alex Forencich
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3401e069d1
|
sync: Set ASYNC_REG in HDL instead of TCL
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-28 20:03:38 -07:00 |
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Alex Forencich
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577c572c5d
|
example: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-28 17:12:55 -07:00 |
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Alex Forencich
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d43569a92a
|
eth: Add taxi_eth_phy_25g_us_gt module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-28 17:12:05 -07:00 |
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Alex Forencich
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8dc33f3a44
|
eth: Use shared counter for fractional part of pause quanta
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-26 20:02:35 -07:00 |
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Alex Forencich
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3dc7e4821d
|
eth: Ensure header pointer is wide enough to clear the entire header before halting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-26 19:31:51 -07:00 |
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Alex Forencich
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be7016991a
|
eth: Fix OS_START block decode issue in xgmii_baser_dec_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-26 19:27:32 -07:00 |
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Alex Forencich
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6584ebb6cd
|
example: Enable statistics strings in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-17 00:34:53 -07:00 |
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Alex Forencich
|
0044782224
|
eth: Remove FIFO pipeline registers for statistics FIFOs in distributed RAM
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-17 00:34:22 -07:00 |
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Alex Forencich
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800c6a9a0b
|
eth: Clean up statistics infrastructure
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 22:44:32 -07:00 |
|
Alex Forencich
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8d7ec01268
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xfcp: Collect statistics strings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 22:42:58 -07:00 |
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Alex Forencich
|
a1832339d2
|
stats: Exclude strings from statistics counts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 22:41:57 -07:00 |
|
Alex Forencich
|
01c0c6cdc6
|
stats: Add strings collector
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 22:40:53 -07:00 |
|
Alex Forencich
|
e6cf1f5850
|
eth: Add statistics strings to Ethernet MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 21:35:50 -07:00 |
|
Alex Forencich
|
031d092513
|
stats: Add string support to statistics collector
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 17:08:52 -07:00 |
|
Alex Forencich
|
e3fcf54466
|
stats: Add gate input to statistics collector
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 11:54:16 -07:00 |
|
Alex Forencich
|
4be054e9b3
|
eth: Reorganize MAC stats module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-15 10:59:35 -07:00 |
|
Alex Forencich
|
99933f3234
|
stats: Optimize zeroing and output logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-14 22:20:39 -07:00 |
|
Alex Forencich
|
b505167348
|
stats: Add defaults for inputs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-14 16:44:03 -07:00 |
|
Alex Forencich
|
1f1c15ba8d
|
stats: Add max increment rate test
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-10 21:59:27 -07:00 |
|
Alex Forencich
|
9dcea3dd23
|
stats: Add register to store dumped value from channel to break timing path
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-10 21:44:55 -07:00 |
|
Alex Forencich
|
8e91c26dbd
|
stats: Simplify statistics collector logic by using a shift register to track updates
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-10 15:16:39 -07:00 |
|
Alex Forencich
|
7128b90c1d
|
stats: Simplify zeroing in statistics collector
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-10 00:20:52 -07:00 |
|
Alex Forencich
|
b5240ac119
|
example/ZCU111: Add XFCP to ZCU111 example design for monitoring and control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 19:24:56 -07:00 |
|
Alex Forencich
|
665599d748
|
example/ZCU102: Add XFCP to ZCU102 example design for monitoring and control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 19:22:16 -07:00 |
|
Alex Forencich
|
28fd0f8cba
|
example/Arty: Arty example design clean-up
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 19:12:57 -07:00 |
|
Alex Forencich
|
d355956b68
|
example/KCU105: Add XFCP to KCU105 example design for monitoring and control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 19:11:54 -07:00 |
|
Alex Forencich
|
50e5dca188
|
example/VCU108: Add XFCP to VCU108 example design for monitoring and control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 18:58:44 -07:00 |
|
Alex Forencich
|
f2b5ea5c0b
|
example/HTG940: Add XFCP to HTG940 example design for monitoring and control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 18:45:55 -07:00 |
|