Alex Forencich
|
31081b6a23
|
eth: Update fb2CG@KU15P example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:49:09 -08:00 |
|
Alex Forencich
|
c2858c183e
|
eth: Fix typo in fb2CG@KU15P example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:28:42 -08:00 |
|
Alex Forencich
|
a7b2db9c20
|
eth: Update Nexus K35-S/K3P-S example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 20:50:32 -08:00 |
|
Alex Forencich
|
ae05128b44
|
eth: Update Nexus K3P-Q example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 20:46:30 -08:00 |
|
Alex Forencich
|
4682591ec3
|
eth: Update ZCU111 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 18:08:19 -08:00 |
|
Alex Forencich
|
3c40ce964b
|
eth: Update AS02MC04 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 17:59:46 -08:00 |
|
Alex Forencich
|
40cc51d062
|
eth: Update ZCU106 example design testbench to test both 32-bit and 64-bit configurations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 15:37:49 -08:00 |
|
Alex Forencich
|
7dbe595e5b
|
eth: Update ADM-PCIE-9V3 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 15:36:49 -08:00 |
|
Alex Forencich
|
77313e1ed0
|
eth: Add example design for Alibaba AS02MC04
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 14:35:33 -08:00 |
|
Alex Forencich
|
3b95e2f279
|
dma: Remove unnecessary handshake condition
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 17:45:54 -08:00 |
|
Alex Forencich
|
b0dd91aa8d
|
dma: Add UltraScale PCIe DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 17:18:26 -08:00 |
|
Alex Forencich
|
14d988d1f2
|
dma: Add AXI DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 12:41:07 -08:00 |
|
Alex Forencich
|
851919f16f
|
dma: Add AXI stream sink DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 21:30:55 -08:00 |
|
Alex Forencich
|
5663572421
|
dma: Add AXI stream source DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 21:30:20 -08:00 |
|
Alex Forencich
|
5b0c83fc57
|
dma: Add AXI streaming DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 17:14:24 -08:00 |
|
Alex Forencich
|
9442bb7fbb
|
dma: Add AXI central DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 11:42:04 -08:00 |
|
Alex Forencich
|
999602cf11
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 09:24:04 -08:00 |
|
Alex Forencich
|
4b7e3d066d
|
dma: Add SV interface for DMA descriptors
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 09:23:46 -08:00 |
|
Alex Forencich
|
4e099af53a
|
math: Add MT19937 Mersenne Twister PRNG module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-15 22:14:21 -07:00 |
|
Alex Forencich
|
7ec62b6b47
|
eth: Push CRC computation logic towards input in 64-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:34:27 -07:00 |
|
Alex Forencich
|
f6bfd0d097
|
eth: Push CRC computation logic towards input in 64-bit XGMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:10:30 -07:00 |
|
Alex Forencich
|
ae53b5d286
|
eth: Push CRC computation logic towards input in 32-bit XGMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:09:59 -07:00 |
|
Alex Forencich
|
adf10be684
|
eth: Remove unused rxc regs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:12:50 -07:00 |
|
Alex Forencich
|
08879e80b8
|
eth: Mask off end of packet when lane swapped
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:12:20 -07:00 |
|
Alex Forencich
|
59a3d5f511
|
eth: Normalize signal and register names in MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:11:27 -07:00 |
|
Alex Forencich
|
2810b72147
|
eth: Decoding is don't care with termination in lane 0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 21:59:20 -07:00 |
|
Alex Forencich
|
caeacadb78
|
eth: Clean up masking, lane 0 never needs to be masked
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 20:06:58 -07:00 |
|
Alex Forencich
|
93ef0f970b
|
eth: Re-nest if statements for termination character handling in 10G RX logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 19:01:47 -07:00 |
|
Alex Forencich
|
e395398666
|
eth: Rework input encoding in BASE-R RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 18:43:20 -07:00 |
|
Alex Forencich
|
7e08164e8d
|
eth: Add term_first_cycle_reg to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 17:01:53 -07:00 |
|
Alex Forencich
|
879b65cc70
|
eth: Normalize CRC register naming in 10G RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 15:54:49 -07:00 |
|
Alex Forencich
|
d0d6747f88
|
eth: Merge lane swapping logic into BASE-R encode logic in 64-bit BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 11:47:21 -07:00 |
|
Alex Forencich
|
0e2acbf482
|
eth: Fix 2D array declarations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 11:02:30 -07:00 |
|
Alex Forencich
|
5dff55ec06
|
lfsr: Remove extraneous data mask init
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 22:08:57 -07:00 |
|
Alex Forencich
|
04df834708
|
eth: Optimize frame length enforcement logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 15:49:51 -07:00 |
|
Alex Forencich
|
8257fdf09e
|
eth: Remove unused encodings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 13:47:52 -07:00 |
|
Alex Forencich
|
144537126a
|
axis: Remove extraneous generate block in async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 23:36:25 -07:00 |
|
Alex Forencich
|
f4e36bd081
|
eth: Optimize padding logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 23:08:11 -07:00 |
|
Alex Forencich
|
7e629d934f
|
Fix TX enable in AXI stream BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 20:44:43 -07:00 |
|
Alex Forencich
|
159c9d6241
|
eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 16:11:07 -07:00 |
|
Alex Forencich
|
76d4465081
|
eth: Convert UltraScale wrapper to use unpacked arrays for channels
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 16:10:37 -07:00 |
|
Alex Forencich
|
a74a49cffb
|
xfcp: Add XFCP module for APB
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 21:01:17 -07:00 |
|
Alex Forencich
|
86f52189b5
|
xfcp: Symlinks for common testbench code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 20:59:58 -07:00 |
|
Alex Forencich
|
8f5a534d35
|
axi: Tie off ruser/buser in AXI lite RAM modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 16:30:32 -07:00 |
|
Alex Forencich
|
bdfc0f120c
|
axi: Tie off ruser/buser in AXI RAM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 16:28:59 -07:00 |
|
Alex Forencich
|
88018ac9e8
|
axi: Add AXI lite to APB adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 16:14:17 -07:00 |
|
Alex Forencich
|
952232ad66
|
apb: Add APB dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 15:25:21 -07:00 |
|
Alex Forencich
|
f25e41de18
|
apb: Add APB RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 15:24:56 -07:00 |
|
Alex Forencich
|
f4f473afeb
|
apb: Add user sideband signals to APB interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 15:19:07 -07:00 |
|
Alex Forencich
|
e836357c33
|
ci: Update packages
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 14:38:49 -07:00 |
|