Alex Forencich
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36ea9fb8d4
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example/Arty: Clean up Arty example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-18 00:55:08 -08:00 |
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Alex Forencich
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db183c7bdd
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Add test durations for pytest-split
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-17 18:10:01 -08:00 |
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Alex Forencich
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6577d016e5
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Run example design testbenches in CI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-17 00:26:06 -08:00 |
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Alex Forencich
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2c6fac0b9d
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-17 00:13:51 -08:00 |
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Alex Forencich
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dd2a0d1bf3
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example: Add example design for Arty A7
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-17 00:13:06 -08:00 |
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Alex Forencich
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c6ca108392
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eth: Clean up testbench clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:45:19 -08:00 |
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Alex Forencich
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689cd34739
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eth: Add additional Ethernet MAC-related timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:30:15 -08:00 |
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Alex Forencich
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1112545d0a
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:22:43 -08:00 |
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Alex Forencich
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94dba88560
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eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:17:42 -08:00 |
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Alex Forencich
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255b26d2f2
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eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:17:22 -08:00 |
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Alex Forencich
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baa5f72a6c
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eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:16:54 -08:00 |
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Alex Forencich
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ffaf05f2d1
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eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:05:59 -08:00 |
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Alex Forencich
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fab49d1435
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eth: Add RGMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:50:42 -08:00 |
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Alex Forencich
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c0583aaff5
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eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:37:12 -08:00 |
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Alex Forencich
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1dc5463f00
|
eth: Add GMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:34:49 -08:00 |
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Alex Forencich
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175230eeaf
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eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 20:46:31 -08:00 |
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Alex Forencich
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af912cc849
|
eth: Add MII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 20:05:41 -08:00 |
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Alex Forencich
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da7fe065cc
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io: Rework generic ODDR implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 19:27:56 -08:00 |
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Alex Forencich
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d01a90298c
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eth: Use correct clock for TX completions in MAC + FIFO testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 18:59:18 -08:00 |
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Alex Forencich
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5c8037093b
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eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 18:06:41 -08:00 |
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Alex Forencich
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e3d8ad8d36
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io: Add source-synchronous IO modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 15:44:34 -08:00 |
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Alex Forencich
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e18a2b3457
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io: Add generic IDDR and ODDR modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 15:41:56 -08:00 |
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Alex Forencich
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51d6919622
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ptp: Add timing constraints for PTP components
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 11:29:57 -08:00 |
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Alex Forencich
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d048a8d7c7
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:23:57 -08:00 |
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Alex Forencich
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9ad43f3433
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 22:13:01 -08:00 |
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Alex Forencich
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fc1e0efad7
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ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 22:07:46 -08:00 |
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Alex Forencich
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ad0d44616b
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ptp: Add PTP TD leaf clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 20:18:17 -08:00 |
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Alex Forencich
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68c547b219
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ptp: Minor cleanup in PTP CDC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 20:17:21 -08:00 |
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Alex Forencich
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2eaa2f64a2
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ptp: Add PTP TD PHC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 17:50:16 -08:00 |
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Alex Forencich
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38a150b87a
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ptp: Add PTP period output module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 17:06:46 -08:00 |
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Alex Forencich
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d1578513c8
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:51:25 -08:00 |
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Alex Forencich
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2abe774f8a
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eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 13:48:54 -08:00 |
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Alex Forencich
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90650aee69
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eth: Add 10G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 13:47:54 -08:00 |
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Alex Forencich
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d76e810033
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axis: Fix parameter sizing in AXI stream FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 13:46:56 -08:00 |
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Alex Forencich
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f356fad6fe
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ptp: Add PTP clock CDC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 12:49:42 -08:00 |
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Alex Forencich
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17b4c37a1e
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ptp: Add PTP clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 10:52:27 -08:00 |
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Alex Forencich
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8a67eaa220
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eth: Clean up testbench parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:35:18 -08:00 |
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Alex Forencich
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04b73e7ddf
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eth: Add 1G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:12:57 -08:00 |
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Alex Forencich
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8f8572bdee
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eth: Add taxi_axis_if to MAC file list files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-11 15:54:15 -08:00 |
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Alex Forencich
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2616e3f3e3
|
eth: Add 10G Ethernet combined MAC+PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:40:50 -08:00 |
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Alex Forencich
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0ddb89b18f
|
eth: Add 10G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:26:03 -08:00 |
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Alex Forencich
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fa73f9c1d5
|
eth: Add 1G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:25:48 -08:00 |
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Alex Forencich
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8d3d703656
|
eth: Add MAC control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 19:59:11 -08:00 |
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Alex Forencich
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96e348ac84
|
eth: Invert TX completion output control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 23:24:28 -08:00 |
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Alex Forencich
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1c381ce22e
|
eth: Enable tuser signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 22:23:03 -08:00 |
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Alex Forencich
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72dabc5a9a
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eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:23 -08:00 |
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Alex Forencich
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2af4e7af3e
|
eth: Add AXI stream 64-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:15 -08:00 |
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Alex Forencich
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a375eb342d
|
eth: Add AXI stream 32-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:06 -08:00 |
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Alex Forencich
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c914adf9f1
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:02:48 -08:00 |
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Alex Forencich
|
e3f047d735
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:27:27 -08:00 |
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