Alex Forencich
|
3519abbee5
|
eth: Add support for 10GBASE-R to KC705 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-09 14:24:05 -08:00 |
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Alex Forencich
|
4e256cfe37
|
eth: Add support for 7-series GTX transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-09 13:39:14 -08:00 |
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Alex Forencich
|
44ebbbbc87
|
eth: KC705 cleanup, add I2C
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-09 13:37:10 -08:00 |
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Alex Forencich
|
6054f76a17
|
eth: Add Ethernet example design for NetFPGA SUME
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 19:46:20 -08:00 |
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Alex Forencich
|
4dbfc4d388
|
eth: Add Ethernet example design for VC709
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 16:06:12 -08:00 |
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Alex Forencich
|
2d061a76f2
|
eth: Add support for 7-series GTH transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 00:39:50 -08:00 |
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Alex Forencich
|
32eed71e89
|
eth: Clean up MAC wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:26:12 -08:00 |
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Alex Forencich
|
1cd6275877
|
eth: Update ZCU111 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:24:00 -08:00 |
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Alex Forencich
|
1e8917affb
|
eth: Update KCU105 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:23:12 -08:00 |
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Alex Forencich
|
cae7053e78
|
eth: Update KC705 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:23:00 -08:00 |
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Alex Forencich
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004246608e
|
Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 02:14:19 -08:00 |
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Alex Forencich
|
5f814e7da8
|
Clean up always blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 01:51:18 -08:00 |
|
Alex Forencich
|
efc907e4c9
|
axis: Add assertions to FIFO modules for USER_EN settings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 17:58:33 -08:00 |
|
Alex Forencich
|
9009880073
|
eth: Enable tuser signal in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 17:44:50 -08:00 |
|
Alex Forencich
|
434f31887e
|
eth: Use tie and null_src modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 09:35:26 -08:00 |
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Alex Forencich
|
c6eac348f6
|
eth: Update HTG-9200 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 00:49:50 -08:00 |
|
Alex Forencich
|
0fe56c5390
|
eth: Update Alveo example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 23:42:03 -08:00 |
|
Alex Forencich
|
b97eb139ca
|
eth: Update XUPP3R/XUSP3S example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 22:02:32 -08:00 |
|
Alex Forencich
|
66a93a734f
|
eth: Update HTG-ZRF8-EM/R2 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:54:04 -08:00 |
|
Alex Forencich
|
06eb4aafcd
|
eth: Update VCU118 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:51:40 -08:00 |
|
Alex Forencich
|
0f5bc4eba8
|
eth: Update VCU108 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:49:33 -08:00 |
|
Alex Forencich
|
31081b6a23
|
eth: Update fb2CG@KU15P example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:49:09 -08:00 |
|
Alex Forencich
|
c2858c183e
|
eth: Fix typo in fb2CG@KU15P example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:28:42 -08:00 |
|
Alex Forencich
|
a7b2db9c20
|
eth: Update Nexus K35-S/K3P-S example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 20:50:32 -08:00 |
|
Alex Forencich
|
ae05128b44
|
eth: Update Nexus K3P-Q example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 20:46:30 -08:00 |
|
Alex Forencich
|
4682591ec3
|
eth: Update ZCU111 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 18:08:19 -08:00 |
|
Alex Forencich
|
3c40ce964b
|
eth: Update AS02MC04 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 17:59:46 -08:00 |
|
Alex Forencich
|
40cc51d062
|
eth: Update ZCU106 example design testbench to test both 32-bit and 64-bit configurations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 15:37:49 -08:00 |
|
Alex Forencich
|
7dbe595e5b
|
eth: Update ADM-PCIE-9V3 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 15:36:49 -08:00 |
|
Alex Forencich
|
77313e1ed0
|
eth: Add example design for Alibaba AS02MC04
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 14:35:33 -08:00 |
|
Alex Forencich
|
3b95e2f279
|
dma: Remove unnecessary handshake condition
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 17:45:54 -08:00 |
|
Alex Forencich
|
b0dd91aa8d
|
dma: Add UltraScale PCIe DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 17:18:26 -08:00 |
|
Alex Forencich
|
14d988d1f2
|
dma: Add AXI DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 12:41:07 -08:00 |
|
Alex Forencich
|
851919f16f
|
dma: Add AXI stream sink DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 21:30:55 -08:00 |
|
Alex Forencich
|
5663572421
|
dma: Add AXI stream source DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 21:30:20 -08:00 |
|
Alex Forencich
|
5b0c83fc57
|
dma: Add AXI streaming DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 17:14:24 -08:00 |
|
Alex Forencich
|
9442bb7fbb
|
dma: Add AXI central DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 11:42:04 -08:00 |
|
Alex Forencich
|
999602cf11
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 09:24:04 -08:00 |
|
Alex Forencich
|
4b7e3d066d
|
dma: Add SV interface for DMA descriptors
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 09:23:46 -08:00 |
|
Alex Forencich
|
4e099af53a
|
math: Add MT19937 Mersenne Twister PRNG module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-15 22:14:21 -07:00 |
|
Alex Forencich
|
7ec62b6b47
|
eth: Push CRC computation logic towards input in 64-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:34:27 -07:00 |
|
Alex Forencich
|
f6bfd0d097
|
eth: Push CRC computation logic towards input in 64-bit XGMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:10:30 -07:00 |
|
Alex Forencich
|
ae53b5d286
|
eth: Push CRC computation logic towards input in 32-bit XGMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:09:59 -07:00 |
|
Alex Forencich
|
adf10be684
|
eth: Remove unused rxc regs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:12:50 -07:00 |
|
Alex Forencich
|
08879e80b8
|
eth: Mask off end of packet when lane swapped
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:12:20 -07:00 |
|
Alex Forencich
|
59a3d5f511
|
eth: Normalize signal and register names in MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:11:27 -07:00 |
|
Alex Forencich
|
2810b72147
|
eth: Decoding is don't care with termination in lane 0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 21:59:20 -07:00 |
|
Alex Forencich
|
caeacadb78
|
eth: Clean up masking, lane 0 never needs to be masked
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 20:06:58 -07:00 |
|
Alex Forencich
|
93ef0f970b
|
eth: Re-nest if statements for termination character handling in 10G RX logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 19:01:47 -07:00 |
|
Alex Forencich
|
e395398666
|
eth: Rework input encoding in BASE-R RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 18:43:20 -07:00 |
|