Alex Forencich
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ecfb50641d
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axis: Fix async FIFO timing constraints when using distributed RAM
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-04-09 14:24:12 -07:00 |
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Alex Forencich
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cf44abae0d
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axis: Use signal sync module for async FIFO output pause
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:13:10 -08:00 |
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Alex Forencich
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181691941f
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eth: Use signal sync module for RGMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:12:50 -08:00 |
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Alex Forencich
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f8d5d6a45e
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eth: Use signal sync module for GMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:12:10 -08:00 |
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Alex Forencich
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64c1cb1e39
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eth: Use signal sync module for internal MAC pause handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 16:27:37 -08:00 |
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Alex Forencich
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6e90f4f0a0
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syn: Add timing constraints for signal synchronizer
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 15:39:00 -08:00 |
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Alex Forencich
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eae85cb8c7
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syn: Clean up timing constraints for reset sync
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 15:38:39 -08:00 |
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Alex Forencich
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6154506c0a
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axis: Use reset synchronizer module in AXI stream async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-20 12:44:23 -08:00 |
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Alex Forencich
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689cd34739
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eth: Add additional Ethernet MAC-related timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:30:15 -08:00 |
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Alex Forencich
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ffaf05f2d1
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eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:05:59 -08:00 |
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Alex Forencich
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fab49d1435
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eth: Add RGMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:50:42 -08:00 |
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Alex Forencich
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c0583aaff5
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eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:37:12 -08:00 |
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Alex Forencich
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51d6919622
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ptp: Add timing constraints for PTP components
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 11:29:57 -08:00 |
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Alex Forencich
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69e5ae8545
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axis: Add AXI stream async FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-06 00:46:39 -08:00 |
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Alex Forencich
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9cc4cbc670
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sync: Add reset synchronizer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:42:47 -08:00 |
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