Alex Forencich
|
c5fea4d920
|
dma: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:04:44 -07:00 |
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Alex Forencich
|
10500e6c6c
|
dma: Add DMA RAM interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:04:22 -07:00 |
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Alex Forencich
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e87e16c299
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axi: Add AXI FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 22:17:53 -07:00 |
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Alex Forencich
|
0080125120
|
axi: Add AXI to AXI lite adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 21:11:20 -07:00 |
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Alex Forencich
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94a821192c
|
axi: Add AXI width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 21:10:08 -07:00 |
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Alex Forencich
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5f6487964e
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axi: Add MAX_BURST_LEN and NARROW_BURST_EN parameters to AXI interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 13:55:33 -07:00 |
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Alex Forencich
|
e43d6acbbd
|
axi: Add AXI lite to AXI adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 13:40:43 -07:00 |
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Alex Forencich
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c22e659259
|
axi: Add AXI lite width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 13:02:27 -07:00 |
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Alex Forencich
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4dd84efd6c
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 18:00:22 -07:00 |
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Alex Forencich
|
bf584147a1
|
pcie: Clean up AXI lite interface width handling in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 17:59:56 -07:00 |
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Alex Forencich
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b3441f6408
|
pcie: Rename enable to en in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 17:59:33 -07:00 |
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Alex Forencich
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63c961cab4
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pcie: Fix some corner cases in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 16:50:31 -07:00 |
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Alex Forencich
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b5c9c02b03
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pcie: Add UltraScale PCIe AXI Lite Master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-25 22:39:28 -07:00 |
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Alex Forencich
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06e6f3e1b4
|
lss: Optimize delay implementation in I2C master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:30:03 -07:00 |
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Alex Forencich
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c2c4f5316d
|
xfcp: Fix width
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:26:25 -07:00 |
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Alex Forencich
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07ae2ba989
|
eth: Add RFDC to ZCU111 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:26:14 -07:00 |
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Alex Forencich
|
4c43b68f94
|
eth: Add 6QSFP FMC support to HTG9200 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 16:24:39 -07:00 |
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Alex Forencich
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cf0ec74849
|
eth: HTG9200 example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 06:37:14 -07:00 |
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Alex Forencich
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5e890bc6cd
|
axis: Add AXI stream tie and null source/sink modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 06:33:21 -07:00 |
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Alex Forencich
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a8dbe26f12
|
zircon: tdest not used on TX path after length/checksum computation, which also extracts the tdest value
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-15 13:36:14 -07:00 |
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Alex Forencich
|
3a07e3e28c
|
zircon: Improve sideband signal handling in length/checksum computation module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-15 13:34:15 -07:00 |
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Alex Forencich
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d0efd5f24c
|
zircon: Connect tdest
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-14 14:11:55 -07:00 |
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Alex Forencich
|
9955b79fcd
|
zircon: Add FIFO configuration parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-13 17:17:34 -07:00 |
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Alex Forencich
|
af8daa89ce
|
zircon: Fix flow control bug in parser
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-13 13:44:49 -07:00 |
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Alex Forencich
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0aad8ef2cc
|
zircon: Fix testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:33:05 -07:00 |
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Alex Forencich
|
e5ce27cc30
|
zircon: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:13:47 -07:00 |
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Alex Forencich
|
67bfb947f4
|
zircon: Add TX buffer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:09:04 -07:00 |
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Alex Forencich
|
18fdf53d5d
|
zircon: Add ingress and egress modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:08:40 -07:00 |
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Alex Forencich
|
48465423fb
|
zircon: Add length and checksum computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:06:12 -07:00 |
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Alex Forencich
|
7c1f2652b6
|
zircon: Add TX deparser module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 14:57:14 -07:00 |
|
Alex Forencich
|
babce69bd0
|
zircon: Add RX parser module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 14:49:22 -07:00 |
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Alex Forencich
|
65cb6124c4
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:20:34 -07:00 |
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Alex Forencich
|
a16a667f81
|
lss: Add I2C init module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:20:21 -07:00 |
|
Alex Forencich
|
d4089096ae
|
example: Add example design for HTG-9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:19:58 -07:00 |
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Alex Forencich
|
467b044e88
|
lss: Add missing file list file handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 15:15:29 -07:00 |
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Alex Forencich
|
89f60f26ff
|
lss: Add some interface configuration checks to I2C modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 14:40:56 -07:00 |
|
Alex Forencich
|
8017534c45
|
lss: Rename I2C data ports to reduce ambiguity
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 14:40:33 -07:00 |
|
Alex Forencich
|
4620370035
|
lss: Add I2C slave AXI lite master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 00:44:14 -07:00 |
|
Alex Forencich
|
37825a02f4
|
lss: Add I2C slave module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 00:22:11 -07:00 |
|
Alex Forencich
|
8bcd7ca037
|
axis: Expand size range for concatenator module tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-31 14:13:13 -07:00 |
|
Alex Forencich
|
933899887a
|
axis: Add AXI stream switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-31 11:47:49 -07:00 |
|
Alex Forencich
|
dd8b2a89ed
|
axis: Remove unnecessary idle cycles in taxi_axis_concat
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 22:03:16 -07:00 |
|
Alex Forencich
|
bd0b0cd75a
|
Update documentation URL
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 19:12:45 -07:00 |
|
Alex Forencich
|
d10e3cf5c0
|
axis: Add AXI stream demultiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 19:10:48 -07:00 |
|
Alex Forencich
|
b266aa2949
|
axis: Add AXI stream concatenator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 18:57:11 -07:00 |
|
Alex Forencich
|
059c7cd5ce
|
axis: Minor cleanup in taxi_axis_mux
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-29 09:43:11 -07:00 |
|
Alex Forencich
|
75a8750679
|
axis: Minor cleanup in taxi_axis_arb_mux
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-29 09:40:03 -07:00 |
|
Alex Forencich
|
2065151c01
|
eth: Update 10G-only example designs to use 32-bit MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 23:19:30 -07:00 |
|
Alex Forencich
|
7031a3f0b1
|
eth: Add 32-bit mode tests for UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 22:19:55 -07:00 |
|
Alex Forencich
|
5b0cae2aac
|
eth: Add 32-bit support to combined MAC+PCS module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:37:34 -07:00 |
|