Alex Forencich
|
7b1ae24d95
|
eth: Report framing and bad block errors in 32-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:34:42 -07:00 |
|
Alex Forencich
|
fd521a1511
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:50 -07:00 |
|
Alex Forencich
|
295dc2dd23
|
eth: Add 32-bit AXI stream BASE-R RX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:09 -07:00 |
|
Alex Forencich
|
ebb8bf0bd4
|
eth: Add 32-bit AXI stream BASE-R TX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:14:30 -07:00 |
|
Alex Forencich
|
6f5adb1b41
|
eth: Reset pack_seq even if the header is not marked as valid
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 16:32:48 -07:00 |
|
Alex Forencich
|
e8cea4c860
|
eth: Use for loop to reduce duplication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 11:50:29 -07:00 |
|
Alex Forencich
|
facdc5fe68
|
eth: Remove extraneous constants
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-16 16:01:12 -07:00 |
|
Alex Forencich
|
17e48c5f51
|
eth: Support 32-bit mode in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:16:58 -07:00 |
|
Alex Forencich
|
6407b4c7f0
|
eth: Support 32-bit sync gearbox in 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:11:26 -07:00 |
|
Alex Forencich
|
ab09ceb891
|
eth: Support 32 bit mode in BASE-R PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:00:14 -07:00 |
|
Alex Forencich
|
e6b5cd6ecd
|
eth: Support 32 bit mode in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:56:03 -07:00 |
|
Alex Forencich
|
70c0e3d52a
|
eth: Fix RX BER monitor when gearbox is enabled
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:54:01 -07:00 |
|
Alex Forencich
|
2e1619a045
|
eth: Connect and tie off txsequence
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 01:20:23 -07:00 |
|
Alex Forencich
|
cc8ec558bf
|
eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-14 22:54:09 -07:00 |
|
Alex Forencich
|
e993a6cfbf
|
eth: Cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 19:38:06 -07:00 |
|
Alex Forencich
|
65eef8b5e8
|
eth: Parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 19:28:21 -07:00 |
|
Alex Forencich
|
eae4d67367
|
eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 17:57:57 -07:00 |
|
Alex Forencich
|
f9041cd9d2
|
eth: Fix multidriven net
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:51:07 -07:00 |
|
Alex Forencich
|
280e5129b8
|
example: Build all MAC variants for ZCU106
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:48:22 -07:00 |
|
Alex Forencich
|
3349561810
|
eth: Remove extraneous defaults
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:45:00 -07:00 |
|
Alex Forencich
|
741615f203
|
eth: Fix parameter name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:40:32 -07:00 |
|
Alex Forencich
|
e846e7f0cd
|
eth: Add gearbox support to 64-bit 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:39:55 -07:00 |
|
Alex Forencich
|
28195390a2
|
eth: Add GBX_CNT to taxi_xgmii_baser_enc_64 testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:35:04 -07:00 |
|
Alex Forencich
|
d4acf48e0a
|
eth: Fix gearbox interface in 10G PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:34:44 -07:00 |
|
Alex Forencich
|
0fd4000f69
|
eth: Support both split and combined MAC/PCS in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 14:31:14 -07:00 |
|
Alex Forencich
|
886aa65522
|
eth: Add testbench for taxi_eth_mac_25g_us module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 10:34:43 -07:00 |
|
Alex Forencich
|
98d06954cc
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 10:28:53 -07:00 |
|
Alex Forencich
|
4e66dd0f98
|
eth: Rename gearbox start signals to sync
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-12 15:45:07 -07:00 |
|
Alex Forencich
|
ca3ee2d197
|
eth: Fix PFC/LFC parameters in 25G MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-12 14:56:55 -07:00 |
|
Alex Forencich
|
a146aeaf21
|
lfsr: Merge output state with data when possible
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 18:48:07 -07:00 |
|
Alex Forencich
|
faa914c828
|
lfsr: Merge input state with data when possible
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 18:30:31 -07:00 |
|
Alex Forencich
|
a4ac9e7bb0
|
lfsr: Add PCIe scramlber sequence as a galois-mode PRBS test
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 13:06:51 -07:00 |
|
Alex Forencich
|
79a1438230
|
lfsr: Remove debug prints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 13:03:10 -07:00 |
|
Alex Forencich
|
f7315b7675
|
lfsr: Clean up LFSR implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-11 00:35:36 -07:00 |
|
Alex Forencich
|
4e7e39828b
|
lfsr: Add tests for PCIe gen 3 scrambler
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-10 23:56:55 -07:00 |
|
Alex Forencich
|
e36ac879f7
|
lfsr: Add support for non-self-synchronizing scrambler, add tests for PCIe gen 1/2 scrambler
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-10 23:20:42 -07:00 |
|
Alex Forencich
|
90780aa0b5
|
lfsr: Fix alignment
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-10 22:41:31 -07:00 |
|
Alex Forencich
|
a1e24f2d7f
|
lfsr: Add input and output enable parameters to LFSR module to remove dead code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-10 19:08:55 -07:00 |
|
Alex Forencich
|
16395bd5cd
|
lss: Fix I2C waveforms
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-10 16:45:27 -07:00 |
|
Alex Forencich
|
3ec52611eb
|
ptp: Adjust testbench thresholds
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-30 22:11:36 -07:00 |
|
Alex Forencich
|
0eec8eb5be
|
ci: Update verilator to 5.034
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-30 21:47:36 -07:00 |
|
Alex Forencich
|
e4762b7a8c
|
eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-30 21:14:54 -07:00 |
|
Alex Forencich
|
f31ba113d2
|
example: Fix KCU105 TX disable pin constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-30 18:54:45 -07:00 |
|
Alex Forencich
|
aa8f19bf3b
|
eth: Reorganize clock enable in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-27 23:56:28 -07:00 |
|
Alex Forencich
|
9bce7f4165
|
eth: Shorten header argument name in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-27 21:27:46 -07:00 |
|
Alex Forencich
|
8a77ee9fc7
|
eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-21 21:06:45 -07:00 |
|
Alex Forencich
|
66b53d98a2
|
Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-18 12:25:59 -07:00 |
|
Alex Forencich
|
8cdae180a1
|
example/Alveo: fix XFCP UART connection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-07 15:19:57 -07:00 |
|
Alex Forencich
|
add5662098
|
eth: Add RX MAC control frame count to MAC statistics counters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-07 14:48:33 -07:00 |
|
Alex Forencich
|
7bfc62d0d2
|
example: Add example design for BittWare XUP-P3R/XUSP3S
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-02 00:08:20 -07:00 |
|