Alex Forencich
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f0f2a25943
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eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-07 16:25:54 -08:00 |
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Alex Forencich
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8046a46680
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eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-07 16:25:06 -08:00 |
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Alex Forencich
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3f501aaac9
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eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-07 16:12:58 -08:00 |
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Alex Forencich
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d52aa2f97e
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axis: Add AXI stream combination async FIFO/adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-06 00:52:04 -08:00 |
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Alex Forencich
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69e5ae8545
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axis: Add AXI stream async FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-06 00:46:39 -08:00 |
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Alex Forencich
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584f2a6542
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eth: Add MAC pause control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 21:11:14 -08:00 |
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Alex Forencich
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f479a85155
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lfsr: Add LFSR descrambler module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 15:29:12 -08:00 |
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Alex Forencich
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e6ea90be36
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lfsr: Add LFSR scrambler module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 15:28:57 -08:00 |
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Alex Forencich
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aeedc3bf7d
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lfsr: Add LFSR PRBS checker module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 15:28:31 -08:00 |
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Alex Forencich
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328a00e30f
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lfsr: Add LFSR PRBS generator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 15:28:08 -08:00 |
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Alex Forencich
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fb69371974
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lfsr: Add LFSR CRC computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 15:27:44 -08:00 |
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Alex Forencich
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e35d2b2c03
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eth: Add 10G PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 17:10:21 -08:00 |
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Alex Forencich
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c6ea4071eb
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eth: Add XGMII/BASE-R encode/decode modules and testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 16:14:32 -08:00 |
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Alex Forencich
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8ee1f5cd18
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lfsr: Add parametrizable LFSR module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 15:39:33 -08:00 |
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Alex Forencich
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f0c9f69987
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axis: Add COBS encoder module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 11:49:50 -08:00 |
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Alex Forencich
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9138a7a51e
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axis: Add COBS decoder module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 11:39:38 -08:00 |
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Alex Forencich
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85eb59f747
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axis: Add AXI stream broadcaster module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 10:38:15 -08:00 |
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Alex Forencich
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e23627c92f
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axis: Add AXI stream combined FIFO/adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:34:34 -08:00 |
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Alex Forencich
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c0a164a1d2
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axis: Add AXI stream adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:33:29 -08:00 |
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Alex Forencich
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03c0883356
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axis: Add AXI stream FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 22:43:17 -08:00 |
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Alex Forencich
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06ee1beb0e
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axis: Add missing parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 22:17:03 -08:00 |
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Alex Forencich
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9590811570
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axis: Add AXI stream pipeline FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 16:35:52 -08:00 |
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Alex Forencich
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47e4658b55
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axis: Add AXI stream pipeline register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 16:35:25 -08:00 |
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Alex Forencich
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e155a917b9
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axis: Remove extraneous parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 16:29:51 -08:00 |
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Alex Forencich
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c4558a02f0
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lss: Add UART module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 15:02:48 -08:00 |
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Alex Forencich
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c7f719b435
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axis: Add AXI stream register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 12:49:08 -08:00 |
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