Alex Forencich ad3042e090 axi: Add AXI lite dual-port RAM module and testbench ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-02-27 00:58:30 -08:00

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taxi_axi_if.sv

axi: Add SV interface for AXI

2025-02-26 20:51:25 -08:00

taxi_axi_ram.sv

axi: Add AXI RAM module and testbench

2025-02-27 00:27:11 -08:00

taxi_axi_register_rd.sv

axi: Add AXI register module and testbench

2025-02-26 21:08:39 -08:00

taxi_axi_register_wr.sv

axi: Add AXI register module and testbench

2025-02-26 21:08:39 -08:00

taxi_axi_register.f

axi: Add AXI register module and testbench

2025-02-26 21:08:39 -08:00

taxi_axi_register.sv

axi: Add AXI register module and testbench

2025-02-26 21:08:39 -08:00

taxi_axil_dp_ram.sv

axi: Add AXI lite dual-port RAM module and testbench

2025-02-27 00:58:30 -08:00

taxi_axil_if.sv

axi: Add SV interface for AXI lite

2025-02-26 20:51:16 -08:00

taxi_axil_ram.sv

axi: Add AXI lite RAM module and testbench

2025-02-27 00:26:03 -08:00

taxi_axil_register_rd.sv

axi: Add AXI lite register module and testbench

2025-02-26 21:02:50 -08:00

taxi_axil_register_wr.sv

axi: Add AXI lite register module and testbench

2025-02-26 21:02:50 -08:00

taxi_axil_register.f

axi: Add AXI lite register module and testbench

2025-02-26 21:02:50 -08:00

taxi_axil_register.sv

axi: Add AXI lite register module and testbench

2025-02-26 21:02:50 -08:00