Add indirect jump

.gitmodules

@@ -1,6 +1,3 @@
 [submodule "sim/sub/taxi"]
 	path = sim/sub/taxi
 	url = git@git.byronlathi.com:bslathi19/taxi.git
-[submodule "sim/sub/verilog-6502"]
-	path = sim/sub/verilog-6502
-	url = git@git.byronlathi.com:third-party/verilog-6502.git

sim/sources.list

@@ -1,18 +1,7 @@
 verilator.vlt
 verilog6502_wrapper_tb.sv
 
-../src/regs/verilog6502_io_regs_pkg.sv
+../src/sources.list
-../src/regs/verilog6502_io_regs.sv
-
-../src/verilog6502_addr_decoder.sv
-../src/verilog6502_internal_memory.sv
-../src/verilog6502_apb_adapter.sv
-../src/verilog6502_external_memory.sv
-../src/verilog6502_wrapper.sv
-
-
-sub/verilog-6502/ALU.v
-sub/verilog-6502/cpu_65c02.v
 
 sub/taxi/src/apb/rtl/taxi_apb_if.sv
 sub/taxi/src/axi/rtl/taxi_axi_if.sv

sim/verilog6502_32bit.yaml

@@ -0,0 +1,9 @@
+tests:
+  - name: "cpu_65c02"
+    toplevel: "cpu_65c02"
+    modules:
+      - "verilog6502_32bit_test"
+    sources: "sources.list"
+    waves: True
+    defines:
+      SIM: "hi"

sim/verilog6502_32bit_test.py

@@ -0,0 +1,341 @@
+import cocotb
+from cocotb.handle import Immediate
+
+from cocotb.clock import Clock
+from cocotb.triggers import Timer, RisingEdge
+
+from collections import defaultdict
+
+CLK_PERIOD = 5
+
+memory = defaultdict(int)
+
+def write_dword(addr: int, data: int):
+    memory[addr + 0] = (data >>  0) & 0xff
+    memory[addr + 1] = (data >>  8) & 0xff
+    memory[addr + 2] = (data >> 16) & 0xff
+    memory[addr + 3] = (data >> 24) & 0xff
+
+def write_byte(addr: int, data: int):
+    memory[addr] = data & 0xff
+
+def write_bytes(addr: int, data: bytes| list[int]):
+    for i, val in enumerate(data):
+        memory[addr + i] = int(val)
+
+async def handle_memory(dut):
+    while True:
+        await RisingEdge(dut.clk)
+        addr = int(dut.AB.value)
+        we = bool(dut.WE.value)
+
+        dut.DI.value = memory[addr]
+
+        if we:
+            memory[addr] = int(dut.DO.value)
+
+async def check_instruction_sequence(dut, instruction_sequence):
+    for expected_output in instruction_sequence:
+        await RisingEdge(dut.clk)
+
+        if expected_output:
+            expected_addr, expected_we, expected_do = expected_output
+            dut_addr = int(dut.AB.value)
+            dut_we = bool(dut.WE.value)
+            dut_do = int(dut.DO.value)
+
+            assert dut_addr == expected_addr
+            assert dut_we == expected_we
+
+            if dut_we:
+                assert dut_do == expected_do
+
+@cocotb.test
+async def test_reset(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x12345678)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        (0x00000100, True,  (int(dut.PC.value) >> 24) & 0xff),  # High addr
+        (0x000001ff, True,  (int(dut.PC.value) >> 16) & 0xff),  # Mid high addr
+        (0x000001fe, True,  (int(dut.PC.value) >>  8) & 0xff),  # Mid low addr
+        (0x000001fd, True,  (int(dut.PC.value) >>  0) & 0xff),  # Low addr
+        (0x000001fc, True,  int(dut.P.value)),                  # Status
+        (0xfffffff4, False, int(dut.regfile.value)),            # read vector byte 0
+        (0xfffffff5, False, int(dut.regfile.value)),            # read vector byte 1
+        (0xfffffff6, False, int(dut.regfile.value)),            # read vector byte 2
+        (0xfffffff7, False, int(dut.regfile.value)),            # read vector byte 3
+        (0x12345678, False, int(dut.regfile.value)),            # Read first instruction
+        (0x12345679, False, int(dut.regfile.value)),            # Read second byte
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+@cocotb.test
+async def test_absolute(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+    # lda $abcd1234
+    # sta $50515253
+    # wai
+    write_bytes(0x200, [0xad, 0x34, 0x12, 0xcd, 0xab])
+    write_bytes(0x205, [0x8d, 0x53, 0x52, 0x51, 0x50])
+    write_byte(0x20a, 0xcb)
+    write_byte(0xabcd1234, 0x55)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),            # Read first instruction
+        (0x00000201, False, None),            # Read address byte 0
+        (0x00000202, False, None),            # Read address byte 1
+        (0x00000203, False, None),            # Read address byte 2
+        (0x00000204, False, None),            # Read address byte 3
+        (0xabcd1234, False, None),            # Read from absolute address
+        (0x00000205, False, None),            # Read second instruction
+        (0x00000206, False, None),            # Read address byte 0
+        (0x00000207, False, None),            # Read address byte 1
+        (0x00000208, False, None),            # Read address byte 2
+        (0x00000209, False, None),            # Read address byte 3
+        (0x50515253, True, 0x55),             # Write to absolute address
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+
+@cocotb.test
+async def test_absolute_x(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+    # ldx #1
+    # lda $abcd1234,x
+    # inx
+    # sta $01020304,x
+    # wai
+    write_bytes(0x200, [0xa2, 0x01])
+    write_bytes(0x202, [0xbd, 0x34, 0x12, 0xcd, 0xab])
+    write_bytes(0x207, [0xe8])
+    write_bytes(0x208, [0x9d, 0x04, 0x03, 0x02, 0x01])
+
+    write_byte(0x20d, 0xcb)
+    write_byte(0xabcd1235, 0xaa)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),            # ldx #1
+        (0x00000201, False, None),            # Immediate
+        (0x00000202, False, None),            # ldx $abcd1234,x
+        (0x00000203, False, None),            # addr 0
+        (0x00000204, False, None),            # addr 1
+        (0x00000205, False, None),            # addr 2
+        (0x00000206, False, None),            # addr 3
+        (0xabcd1235, False, None),            # Read from address
+        (0x00000207, False, None),            # inx
+        (0x00000208, False, None),            # sta $01020304,x
+        (0x00000208, False, None),            # store reg
+        (0x00000209, False, None),            # addr 0
+        (0x0000020a, False, None),            # addr 1
+        (0x0000020b, False, None),            # addr 2
+        (0x0000020c, False, None),            # addr 3
+        (0x01020306, False, None),            # Write to address
+        (0x01020306, True, 0xaa),             # Write to address
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+
+@cocotb.test
+async def test_absolute_y(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+    # ldy #1
+    # lda $abcd1234,y
+    # iny
+    # sta $01020304,y
+    # wai
+    write_bytes(0x200, [0xa0, 0x01])
+    write_bytes(0x202, [0xb9, 0x34, 0x12, 0xcd, 0xab])
+    write_bytes(0x207, [0xc8])
+    write_bytes(0x208, [0x99, 0x04, 0x03, 0x02, 0x01])
+
+    write_byte(0x20d, 0xcb)
+    write_byte(0xabcd1235, 0xaa)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),            # ldx #1
+        (0x00000201, False, None),            # Immediate
+        (0x00000202, False, None),            # ldx $abcd1234,x
+        (0x00000203, False, None),            # addr 0
+        (0x00000204, False, None),            # addr 1
+        (0x00000205, False, None),            # addr 2
+        (0x00000206, False, None),            # addr 3
+        (0xabcd1235, False, None),            # Read from address
+        (0x00000207, False, None),            # inx
+        (0x00000208, False, None),            # sta $01020304,x
+        (0x00000208, False, None),            # store reg
+        (0x00000209, False, None),            # addr 0
+        (0x0000020a, False, None),            # addr 1
+        (0x0000020b, False, None),            # addr 2
+        (0x0000020c, False, None),            # addr 3
+        (0x01020306, False, None),            # Write to address
+        (0x01020306, True, 0xaa),             # Write to address
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+
+@cocotb.test
+async def test_absolute_x_indirect(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+    # ldx #1
+    # jmp ($deadbeef,x)
+    write_bytes(0x200, [0xa2, 0x01])
+    write_bytes(0x202, [0x7c, 0xef, 0xbe, 0xad, 0xde])
+    write_byte(0xbeefb055, 0xcb)
+
+    write_dword(0xdeadbeef + 1, 0xbeefb055)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),            # ldx #1
+        (0x00000201, False, None),            # Immediate
+        (0x00000202, False, None),            # jmp ($deadbeef,x)
+        (0x00000203, False, None),            # addr 0
+        (0x00000204, False, None),            # addr 1
+        (0x00000205, False, None),            # addr 2
+        (0x00000206, False, None),            # addr 3
+        (0xdeadbef0, False, None),            # addr 0
+        (0xdeadbef1, False, None),            # addr 1
+        (0xdeadbef2, False, None),            # addr 2
+        (0xdeadbef3, False, None),            # addr 3
+        (0xbeefb055, False, None),            # target
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+
+@cocotb.test
+async def test_indirect(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+    # jmp ($deadbeef)
+    write_bytes(0x200, [0x6c, 0xef, 0xbe, 0xad, 0xde])
+    write_byte(0xbeefb055, 0xcb)
+
+    write_dword(0xdeadbeef, 0xbeefb055)
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),            # jmp ($deadbeef)
+        (0x00000201, False, None),            # addr 0
+        (0x00000202, False, None),            # addr 1
+        (0x00000203, False, None),            # addr 2
+        (0x00000204, False, None),            # addr 3
+        (0xdeadbeef, False, None),            # addr 0
+        (0xdeadbef0, False, None),            # addr 1
+        (0xdeadbef1, False, None),            # addr 2
+        (0xdeadbef2, False, None),            # addr 3
+        (0xbeefb055, False, None),            # target
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)

src/ALU.v

@@ -0,0 +1,108 @@
+/*
+ * ALU.
+ *
+ * AI and BI are 8 bit inputs. Result in OUT.
+ * CI is Carry In.
+ * CO is Carry Out.
+ *
+ * op[3:0] is defined as follows:
+ *
+ * 0011   AI + BI
+ * 0111   AI - BI
+ * 1011   AI + AI
+ * 1100   AI | BI
+ * 1101   AI & BI
+ * 1110   AI ^ BI
+ * 1111   AI
+ *
+ */
+
+module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
+	input clk;
+	input right;
+	input [3:0] op;		// operation
+	input [7:0] AI;
+	input [7:0] BI;
+	input CI;
+	input BCD;		// BCD style carry
+	output [7:0] OUT;
+	output CO;
+	output V;
+	output Z;
+	output N;
+	output HC;
+	input RDY;
+
+reg [7:0] OUT;
+reg CO;
+wire V;
+wire Z;
+reg N;
+reg HC;
+
+reg AI7;
+reg BI7;
+reg [8:0] temp_logic;
+reg [7:0] temp_BI;
+reg [4:0] temp_l;
+reg [4:0] temp_h;
+wire [8:0] temp = { temp_h, temp_l[3:0] };
+wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
+
+// calculate the logic operations. The 'case' can be done in 1 LUT per
+// bit. The 'right' shift is a simple mux that can be implemented by
+// F5MUX.
+always @*  begin
+	case( op[1:0] )
+	    2'b00: temp_logic = AI | BI;
+	    2'b01: temp_logic = AI & BI;
+	    2'b10: temp_logic = AI ^ BI;
+	    2'b11: temp_logic = AI;
+	endcase
+
+	if( right )
+	    temp_logic = { AI[0], CI, AI[7:1] };
+end
+
+// Add logic result to BI input. This only makes sense when logic = AI.
+// This stage can be done in 1 LUT per bit, using carry chain logic.
+always @* begin
+	case( op[3:2] )
+	    2'b00: temp_BI = BI;	// A+B
+	    2'b01: temp_BI = ~BI;	// A-B
+	    2'b10: temp_BI = temp_logic;	// A+A
+	    2'b11: temp_BI = 0;		// A+0
+	endcase	
+end
+
+// HC9 is the half carry bit when doing BCD add
+wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
+
+// CO9 is the carry-out bit when doing BCD add
+wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
+
+// combined half carry bit
+wire temp_HC = temp_l[4] | HC9;
+
+// perform the addition as 2 separate nibble, so we get
+// access to the half carry flag
+always @* begin
+	temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
+	temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
+end
+
+// calculate the flags 
+always @(posedge clk)
+    if( RDY ) begin
+	AI7 <= AI[7];
+	BI7 <= temp_BI[7];
+	OUT <= temp[7:0];
+	CO  <= temp[8] | CO9;
+	N   <= temp[7];
+	HC  <= temp_HC;
+    end
+
+assign V = AI7 ^ BI7 ^ CO ^ N;
+assign Z = ~|OUT;
+
+endmodule

src/sources.list

@@ -0,0 +1,11 @@
+regs/verilog6502_io_regs_pkg.sv
+regs/verilog6502_io_regs.sv
+verilog6502_addr_decoder.sv
+verilog6502_internal_memory.sv
+verilog6502_apb_adapter.sv
+verilog6502_external_memory.sv
+verilog6502_wrapper.sv
+
+
+ALU.v
+cpu_65c02.v