Add some stuff related to cache

sim/application_wrapper/cache/application_wrapper_cache_l1_test.py

@@ -0,0 +1,19 @@
+import cocotb
+from cocotb.handle import Immediate
+
+from cocotb.clock import Clock
+from cocotb.triggers import Timer, RisingEdge, FallingEdge, with_timeout
+
+
+CLK_PERIOD = 5
+
+@cocotb.test
+async def sanity_test(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await Timer(1, "us")

sim/application_wrapper/cache/cache.yaml

@@ -0,0 +1,7 @@
+tests:
+  - name: "application_wrapper_cache_l1_test"
+    toplevel: "application_wrapper_cache_l1"
+    modules:
+      - "application_wrapper_cache_l1_test"
+    sources: "sources.list"
+    waves: True

sim/application_wrapper/cache/sources.list

@@ -0,0 +1 @@
+../../../src/application_wrapper/sources.list

sim/embedded_wrapper/verilog6502_32bit.yaml

@@ -3,7 +3,7 @@ tests:
     toplevel: "cpu_65c02"
     modules:
       - "verilog6502_32bit_test"
-    sources: "sources.list"
+    sources: "../sources.list"
     waves: True
     defines:
       SIM: "hi"

sim/embedded_wrapper/verilog6502_32bit_asm.yaml

@@ -3,7 +3,7 @@ tests:
     toplevel: "cpu_65c02"
     modules:
       - "verilog6502_32bit_asm_test"
-    sources: "sources.list"
+    sources: "../sources.list"
     waves: True
     defines:
       SIM: "hi"

sim/embedded_wrapper/verilog6502_wrapper.yaml

@@ -3,7 +3,7 @@ tests:
     toplevel: "verilog6502_wrapper_tb"
     modules:
       - "verilog6502_wrapper_test"
-    sources: "sources.list"
+    sources: "../sources.list"
     waves: True
     defines:
       SIM: "hi"

sim/embedded_wrapper/verilog6502_wrapper_tb.sv

@@ -14,7 +14,7 @@ logic i_irq_ext;
 logic i_nmi_ext;
 
 
-verilog6502_wrapper u_dut(
+verilog6502_embedded_wrapper u_dut(
     .clk(clk),
     .rst(rst),
     .s_apb(s_apb),

sim/sources.list

@@ -1,5 +1,5 @@
 verilator.vlt
-verilog6502_wrapper_tb.sv
+embedded_wrapper/verilog6502_wrapper_tb.sv
 
 ../src/sources.list
 

src/application_wrapper/application_wrapper_top.sv

@@ -0,0 +1,3 @@
+module application_wrapper_top();
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_l1.sv

@@ -0,0 +1,108 @@
+import application_wrapper_cache_pkg::*;
+
+module application_wrapper_cache_l1 #(
+    parameter CACHELINE_SIZE = 64,
+    parameter CACHELINE_COUNT = 64,
+    localparam ADDR_WIDTH = 32
+)(
+    input  logic                    i_clk,
+    input  logic                    i_rst,
+
+    /* CPU Interface */
+    input  logic [ADDR_WIDTH-1:0]   i_addr,
+    input  logic                    i_we,
+    input  logic [7:0]              i_data,
+    output logic [7:0]              o_data,
+
+    input  logic                    i_rdy,
+    output logic                    o_rdy,
+
+    /* MMU Interface */
+    input  logic [ADDR_WIDTH-1:0]   i_phys_address,
+    output page_table_entry_t       i_table_entry,
+    input  logic                    i_mmu_valid,
+
+    /* Higher level cache interface */
+    output logic [ADDR_WIDTH-1:0]   o_addr,
+    output logic [1:0]              o_cache_cmd,
+    output logic                    o_cache_valid,
+
+    output logic [63:0]             o_cache_data,
+    input  logic [31:0]             i_cache_data,
+    input  logic                    i_cache_rdy
+);
+
+// we have 32 bit addresses, 64 byte cache lines, and 64 total lines.
+// Thats 6 bit for offset, 6 bit for index, and 20 bit for cache.
+
+// cache is virtually indexed, physically tagged
+
+localparam OFFSET_W = $clog2(CACHELINE_SIZE);
+localparam INDEX_W = $clog2(CACHELINE_COUNT);
+localparam TAG_W = ADDR_WIDTH - INDEX_W - OFFSET_W;
+localparam META_W = 3; // valid, unique, clean
+
+logic [OFFSET_W-1:0] offset;
+logic [INDEX_W-1:0] index;
+logic [TAG_W-1:0] tag;
+
+assign offset = i_addr[OFFSET_W-1:0];
+assign index = i_addr[INDEX_W+OFFSET_W-1:OFFSET_W];
+assign tag = i_addr[INDEX_W+OFFSET_W+TAG_W-1:INDEX_W+OFFSET_W];
+
+// cacheline size is in bytes, not bits
+// direct mapped cache, read one line so we have data ready if its a hit.
+logic [CACHELINE_SIZE*8-1:0] data_array [CACHELINE_COUNT];
+logic [META_W+TAG_W-1:0] meta_tag_array [CACHELINE_COUNT];
+
+enum logic [1:0] {IDLE, READY, EVICT, READ} state, state_next;
+
+always_ff @(posedge i_clk) begin
+    if (i_rst) begin
+        state <= IDLE;
+    end else begin
+        state <= state_next;
+    end
+end
+
+always_comb begin
+    state_next = state;
+
+    o_rdy = '0;
+
+    case (state)
+        IDLE: begin
+            state_next = READY;
+        end
+
+        READY: begin
+            o_rdy = '1;
+        end
+
+        EVICT: begin
+
+        end
+
+        READ: begin
+
+        end
+    endcase
+end
+
+/*
+
+    In the ready state, we read from the data array and if the line is valid
+    and the tag matches with the address, we present the data to the cpu.
+    Otherwise, we lower o_rdy and send the request to the higher level cache.
+
+    If what we read was valid but the tag didn't match, then we need to evict it.
+    If the line was not valid, then we don't need to evict it and can just request
+    the new data.
+
+    One thing that we also need is an MMU. The TLB can be 1 cycle, then if the TLB
+    says that we are allowed to read from the cache, we can read from the cache.
+*/
+
+
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_pkg.sv

@@ -0,0 +1,13 @@
+package application_wrapper_cache_pkg;
+
+    typedef struct {
+        logic cache_disable;
+        logic read_eanble;
+        logic write_enable;
+        logic execute_enable;
+        logic supervisor;
+        logic present;
+        logic write_through;
+    } page_table_entry_t;
+
+endpackage

src/application_wrapper/cache/application_wrapper_mmu.sv

@@ -0,0 +1,21 @@
+import application_wrapper_cache_pkg::*;
+
+module application_wrapper_mmu #(
+    parameter TLB_COUNT = 32,
+    parameter ADDR_WIDTH = 32,
+    parameter LOG2_PAGE_SIZE = 12
+) (
+    input  logic                    i_clk,
+    input  logic                    i_rst,
+
+    input  logic [ADDR_WIDTH-1:0]   i_cpu_addr,
+    input                           i_we,
+    input                           i_rdy,
+    input                           o_rdy,
+
+    output logic [ADDR_WIDTH-1:0]   o_phys_address,
+    output page_table_entry_t       o_table_entry,
+    output logic                    o_mmu_valid
+);
+
+endmodule

src/application_wrapper/sources.list

@@ -0,0 +1,6 @@
+cache/application_wrapper_cache_pkg.sv
+cache/application_wrapper_cache_l1.sv
+cache/application_wrapper_mmu.sv
+cache/application_wrapper_cache_top.sv
+
+application_wrapper_top.sv

src/embedded_wrapper/verilog6502_embedded_wrapper.sv

@@ -7,7 +7,7 @@
 // 0x00010000-0xFFFFEFFF    External AXI
 // 0xFFFFF000-0xFFFFFFFF    Processor IO 
 
-module verilog6502_wrapper(
+module verilog6502_embedded_wrapper(
     input   clk,
     input   rst,
 

src/fpga6502.sv

@@ -1,387 +0,0 @@
-module fpga6502 (
-    output		    jtagCtrl_tdi,
-    input		    jtagCtrl_tdo,
-    output		    jtagCtrl_enable,
-    output		    jtagCtrl_capture,
-    output		    jtagCtrl_shift,
-    output		    jtagCtrl_update,
-    output		    jtagCtrl_reset,
-    input		    ut_jtagCtrl_tdi,
-    output		    ut_jtagCtrl_tdo,
-    input		    ut_jtagCtrl_enable,
-    input		    ut_jtagCtrl_capture,
-    input		    ut_jtagCtrl_shift,
-    input		    ut_jtagCtrl_update,
-    input		    ut_jtagCtrl_reset,
-    input		    io_cfuClk,
-    input		    io_cfuReset,
-    input		    cpu0_customInstruction_cmd_valid,
-    output		    cpu0_customInstruction_cmd_ready,
-    input [9:0]     cpu0_customInstruction_function_id,
-    input [31:0]    cpu0_customInstruction_inputs_0,
-    input [31:0]    cpu0_customInstruction_inputs_1,
-    output		    cpu0_customInstruction_rsp_valid,
-    input		    cpu0_customInstruction_rsp_ready,
-    output [31:0]   cpu0_customInstruction_outputs_0,
-    input		    cpu1_customInstruction_cmd_valid,
-    output		    cpu1_customInstruction_cmd_ready,
-    input [9:0]     cpu1_customInstruction_function_id,
-    input [31:0]    cpu1_customInstruction_inputs_0,
-    input [31:0]    cpu1_customInstruction_inputs_1,
-    output		    cpu1_customInstruction_rsp_valid,
-    input		    cpu1_customInstruction_rsp_ready,
-    output [31:0]   cpu1_customInstruction_outputs_0,
-    input		    cpu2_customInstruction_cmd_valid,
-    output		    cpu2_customInstruction_cmd_ready,
-    input [9:0]     cpu2_customInstruction_function_id,
-    input [31:0]    cpu2_customInstruction_inputs_0,
-    input [31:0]    cpu2_customInstruction_inputs_1,
-    output		    cpu2_customInstruction_rsp_valid,
-    input		    cpu2_customInstruction_rsp_ready,
-    output [31:0]   cpu2_customInstruction_outputs_0,
-    input		    cpu3_customInstruction_cmd_valid,
-    output		    cpu3_customInstruction_cmd_ready,
-    input [9:0]     cpu3_customInstruction_function_id,
-    input [31:0]    cpu3_customInstruction_inputs_0,
-    input [31:0]    cpu3_customInstruction_inputs_1,
-    output		    cpu3_customInstruction_rsp_valid,
-    input		    cpu3_customInstruction_rsp_ready,
-    output [31:0]   cpu3_customInstruction_outputs_0,
-    output		    io_ddrMasters_0_aw_valid,
-    input		    io_ddrMasters_0_aw_ready,
-    output [31:0]   io_ddrMasters_0_aw_payload_addr,
-    output [3:0]    io_ddrMasters_0_aw_payload_id,
-    output [3:0]    io_ddrMasters_0_aw_payload_region,
-    output [7:0]    io_ddrMasters_0_aw_payload_len,
-    output [2:0]    io_ddrMasters_0_aw_payload_size,
-    output [1:0]    io_ddrMasters_0_aw_payload_burst,
-    output		    io_ddrMasters_0_aw_payload_lock,
-    output [3:0]    io_ddrMasters_0_aw_payload_cache,
-    output [3:0]    io_ddrMasters_0_aw_payload_qos,
-    output [2:0]    io_ddrMasters_0_aw_payload_prot,
-    output		    io_ddrMasters_0_aw_payload_allStrb,
-    output		    io_ddrMasters_0_w_valid,
-    input		    io_ddrMasters_0_w_ready,
-    output [127:0]  io_ddrMasters_0_w_payload_data,
-    output [15:0]   io_ddrMasters_0_w_payload_strb,
-    output		    io_ddrMasters_0_w_payload_last,
-    input		    io_ddrMasters_0_b_valid,
-    output		    io_ddrMasters_0_b_ready,
-    input [3:0]     io_ddrMasters_0_b_payload_id,
-    input [1:0]     io_ddrMasters_0_b_payload_resp,
-    output		    io_ddrMasters_0_ar_valid,
-    input		    io_ddrMasters_0_ar_ready,
-    output [31:0]   io_ddrMasters_0_ar_payload_addr,
-    output [3:0]    io_ddrMasters_0_ar_payload_id,
-    output [3:0]    io_ddrMasters_0_ar_payload_region,
-    output [7:0]    io_ddrMasters_0_ar_payload_len,
-    output [2:0]    io_ddrMasters_0_ar_payload_size,
-    output [1:0]    io_ddrMasters_0_ar_payload_burst,
-    output		    io_ddrMasters_0_ar_payload_lock,
-    output [3:0]    io_ddrMasters_0_ar_payload_cache,
-    output [3:0]    io_ddrMasters_0_ar_payload_qos,
-    output [2:0]    io_ddrMasters_0_ar_payload_prot,
-    input		    io_ddrMasters_0_r_valid,
-    output		    io_ddrMasters_0_r_ready,
-    input [127:0]   io_ddrMasters_0_r_payload_data,
-    input [3:0]     io_ddrMasters_0_r_payload_id,
-    input [1:0]     io_ddrMasters_0_r_payload_resp,
-    input		    io_ddrMasters_0_r_payload_last,
-    input		    io_ddrMasters_0_clk,
-    input		    io_ddrMasters_0_reset,
-    output          io_ddrMasters_memCheck_pass,
-    output		    userInterruptA,
-    output		    userInterruptB,
-    output		    userInterruptC,
-    output		    userInterruptD,
-    output		    userInterruptE,
-    output		    userInterruptF,
-    output		    userInterruptH,
-    output		    userInterruptG,
-    output          userInterruptI,
-    input [3:0]     system_gpio_0_io_read,
-    output [3:0]    system_gpio_0_io_write,
-    output [3:0]    system_gpio_0_io_writeEnable,
-    output		    system_uart_0_io_txd,
-    input		    system_uart_0_io_rxd,
-    output		    system_spi_0_io_sclk_write,
-    output		    system_spi_0_io_data_0_writeEnable,
-    input		    system_spi_0_io_data_0_read,
-    output		    system_spi_0_io_data_0_write,
-    output		    system_spi_0_io_data_1_writeEnable,
-    input		    system_spi_0_io_data_1_read,
-    output		    system_spi_0_io_data_1_write,
-    output		    system_spi_0_io_data_2_writeEnable,
-    input		    system_spi_0_io_data_2_read,
-    output		    system_spi_0_io_data_2_write,
-    output		    system_spi_0_io_data_3_writeEnable,
-    input		    system_spi_0_io_data_3_read,
-    output		    system_spi_0_io_data_3_write,
-    output [3:0]    system_spi_0_io_ss,
-    output		    system_i2c_0_io_sda_writeEnable,
-    output		    system_i2c_0_io_sda_write,
-    input		    system_i2c_0_io_sda_read,
-    output		    system_i2c_0_io_scl_writeEnable,
-    output		    system_i2c_0_io_scl_write,
-    input		    system_i2c_0_io_scl_read,
-    input [31:0]    axiA_awaddr,
-    input [7:0]	    axiA_awlen,
-    input [2:0]	    axiA_awsize,
-    input [1:0]	    axiA_awburst,
-    input		    axiA_awlock,
-    input [3:0]	    axiA_awcache,
-    input [2:0]	    axiA_awprot,
-    input [3:0]	    axiA_awqos,
-    input [3:0]	    axiA_awregion,
-    input		    axiA_awvalid,
-    output		    axiA_awready,
-    input [31:0]    axiA_wdata,
-    input [3:0]     axiA_wstrb,
-    input		    axiA_wvalid,
-    input		    axiA_wlast,
-    output		    axiA_wready,
-    output [1:0]    axiA_bresp,
-    output		    axiA_bvalid,
-    input		    axiA_bready,
-    input [31:0]    axiA_araddr,
-    input [7:0]	    axiA_arlen,
-    input [2:0]	    axiA_arsize,
-    input [1:0]	    axiA_arburst,
-    input		    axiA_arlock,
-    input [3:0]	    axiA_arcache,
-    input [2:0]	    axiA_arprot,
-    input [3:0]	    axiA_arqos,
-    input [3:0]	    axiA_arregion,
-    input		    axiA_arvalid,
-    output		    axiA_arready,
-    output [31:0]   axiA_rdata,
-    output [1:0]    axiA_rresp,
-    output		    axiA_rlast,
-    output		    axiA_rvalid,
-    input		    axiA_rready,
-    output          axiAInterrupt,
-    input           cfg_done,
-    output          cfg_start,
-    output          cfg_sel,
-    output          cfg_reset,
-    input		    io_peripheralClk,
-    input           io_peripheralReset,
-    output          io_asyncReset,
-    input           io_gpio_sw_n, 
-    input           pll_peripheral_locked,
-    input           pll_system_locked,
-    input           pll_tse_locked,
-    //  SDHC
-    input           sd_base_clk, 
-    output          sd_clk_hi,
-    output          sd_clk_lo,
-    input           sd_cmd_i,
-    output          sd_cmd_o,
-    output          sd_cmd_oe,
-    input  [3:0]    sd_dat_i,
-    output [3:0]    sd_dat_o,
-    output [3:0]    sd_dat_oe,
-    input           sd_cd_n, 
-    input           sd_wp,
-    // TSEMAC
-    input           io_tseClk,
-    // MAC 
-    output [3:0]    rgmii_txd_HI,
-    output [3:0]    rgmii_txd_LO,
-    output          rgmii_tx_ctl_HI,
-    output          rgmii_tx_ctl_LO,
-    output          rgmii_txc_HI,
-    output          rgmii_txc_LO,
-    input  [3:0]    rgmii_rxd_HI,
-    input  [3:0]    rgmii_rxd_LO,
-    input           rgmii_rx_ctl_HI,
-    input           rgmii_rx_ctl_LO,
-    input           mux_clk,
-    output [1:0]    mux_clk_sw,
-    // PHY
-    output          phy_rst,
-    input           phy_mdi,
-    output          phy_mdo,
-    output          phy_mdo_en,
-    output          phy_mdc,
-    input           rgmii_rxc,      
-    input           rgmii_rxc_slow
-);
-
-
-
-top_soc u_top_soc (
-    .jtagCtrl_tdi       (jtagCtrl_tdi),
-    .jtagCtrl_tdo    (jtagCtrl_tdo),
-    .jtagCtrl_enable (jtagCtrl_enable),
-    .jtagCtrl_capture    (jtagCtrl_capture),
-    .jtagCtrl_shift  (jtagCtrl_shift),
-    .jtagCtrl_update (jtagCtrl_update),
-    .jtagCtrl_reset  (jtagCtrl_reset),
-    .ut_jtagCtrl_tdi (ut_jtagCtrl_tdi),
-    .ut_jtagCtrl_tdo (ut_jtagCtrl_tdo),
-    .ut_jtagCtrl_enable  (ut_jtagCtrl_enable),
-    .ut_jtagCtrl_capture (ut_jtagCtrl_capture),
-    .ut_jtagCtrl_shift   (ut_jtagCtrl_shift),
-    .ut_jtagCtrl_update  (ut_jtagCtrl_update),
-    .ut_jtagCtrl_reset   (ut_jtagCtrl_reset),
-    .io_cfuClk   (io_cfuClk),
-    .io_cfuReset (io_cfuReset),
-    .io_ddrMasters_0_aw_valid           (io_ddrMasters_0_aw_valid),
-    .io_ddrMasters_0_aw_ready           (io_ddrMasters_0_aw_ready),
-    .io_ddrMasters_0_aw_payload_addr    (io_ddrMasters_0_aw_payload_addr),
-    .io_ddrMasters_0_aw_payload_id      (io_ddrMasters_0_aw_payload_id),
-    .io_ddrMasters_0_aw_payload_region  (io_ddrMasters_0_aw_payload_region),
-    .io_ddrMasters_0_aw_payload_len     (io_ddrMasters_0_aw_payload_len),
-    .io_ddrMasters_0_aw_payload_size    (io_ddrMasters_0_aw_payload_size),
-    .io_ddrMasters_0_aw_payload_burst   (io_ddrMasters_0_aw_payload_burst),
-    .io_ddrMasters_0_aw_payload_lock    (io_ddrMasters_0_aw_payload_lock),
-    .io_ddrMasters_0_aw_payload_cache   (io_ddrMasters_0_aw_payload_cache),
-    .io_ddrMasters_0_aw_payload_qos     (io_ddrMasters_0_aw_payload_qos),
-    .io_ddrMasters_0_aw_payload_prot    (io_ddrMasters_0_aw_payload_prot),
-    .io_ddrMasters_0_aw_payload_allStrb (io_ddrMasters_0_aw_payload_allStrb),
-    .io_ddrMasters_0_w_valid            (io_ddrMasters_0_w_valid),
-    .io_ddrMasters_0_w_ready            (io_ddrMasters_0_w_ready),
-    .io_ddrMasters_0_w_payload_data     (io_ddrMasters_0_w_payload_data),
-    .io_ddrMasters_0_w_payload_strb     (io_ddrMasters_0_w_payload_strb),
-    .io_ddrMasters_0_w_payload_last     (io_ddrMasters_0_w_payload_last),
-    .io_ddrMasters_0_b_valid            (io_ddrMasters_0_b_valid),
-    .io_ddrMasters_0_b_ready            (io_ddrMasters_0_b_ready),
-    .io_ddrMasters_0_b_payload_id       (io_ddrMasters_0_b_payload_id),
-    .io_ddrMasters_0_b_payload_resp     (io_ddrMasters_0_b_payload_resp),
-    .io_ddrMasters_0_ar_valid           (io_ddrMasters_0_ar_valid),
-    .io_ddrMasters_0_ar_ready           (io_ddrMasters_0_ar_ready),
-    .io_ddrMasters_0_ar_payload_addr    (io_ddrMasters_0_ar_payload_addr),
-    .io_ddrMasters_0_ar_payload_id      (io_ddrMasters_0_ar_payload_id),
-    .io_ddrMasters_0_ar_payload_region  (io_ddrMasters_0_ar_payload_region),
-    .io_ddrMasters_0_ar_payload_len     (io_ddrMasters_0_ar_payload_len),
-    .io_ddrMasters_0_ar_payload_size    (io_ddrMasters_0_ar_payload_size),
-    .io_ddrMasters_0_ar_payload_burst   (io_ddrMasters_0_ar_payload_burst),
-    .io_ddrMasters_0_ar_payload_lock    (io_ddrMasters_0_ar_payload_lock),
-    .io_ddrMasters_0_ar_payload_cache   (io_ddrMasters_0_ar_payload_cache),
-    .io_ddrMasters_0_ar_payload_qos     (io_ddrMasters_0_ar_payload_qos),
-    .io_ddrMasters_0_ar_payload_prot    (io_ddrMasters_0_ar_payload_prot),
-    .io_ddrMasters_0_r_valid            (io_ddrMasters_0_r_valid),
-    .io_ddrMasters_0_r_ready            (io_ddrMasters_0_r_ready),
-    .io_ddrMasters_0_r_payload_data     (io_ddrMasters_0_r_payload_data),
-    .io_ddrMasters_0_r_payload_id       (io_ddrMasters_0_r_payload_id),
-    .io_ddrMasters_0_r_payload_resp     (io_ddrMasters_0_r_payload_resp),
-    .io_ddrMasters_0_r_payload_last     (io_ddrMasters_0_r_payload_last),
-    .io_ddrMasters_0_clk                (io_ddrMasters_0_clk),
-    .io_ddrMasters_0_reset              (io_ddrMasters_0_reset),
-    .io_ddrMasters_memCheck_pass        (io_ddrMasters_memCheck_pass),
-    .userInterruptA                     (userInterruptA),
-    .userInterruptB                     (userInterruptB),
-    .userInterruptC                     (userInterruptC),
-    .userInterruptD                     (userInterruptD),
-    .userInterruptE                     (userInterruptE),
-    .userInterruptF                     (userInterruptF),
-    .userInterruptH                     (userInterruptH),
-    .userInterruptG                     (userInterruptG),
-    .userInterruptI                     (userInterruptI),
-    .system_gpio_0_io_read              (system_gpio_0_io_read),
-    .system_gpio_0_io_write             (system_gpio_0_io_write),
-    .system_gpio_0_io_writeEnable       (system_gpio_0_io_writeEnable),
-    .system_uart_0_io_txd               (system_uart_0_io_txd),
-    .system_uart_0_io_rxd               (system_uart_0_io_rxd),
-    .system_spi_0_io_sclk_write         (system_spi_0_io_sclk_write),
-    .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable),
-    .system_spi_0_io_data_0_read        (system_spi_0_io_data_0_read),
-    .system_spi_0_io_data_0_write       (system_spi_0_io_data_0_write),
-    .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable),
-    .system_spi_0_io_data_1_read        (system_spi_0_io_data_1_read),
-    .system_spi_0_io_data_1_write       (system_spi_0_io_data_1_write),
-    .system_spi_0_io_data_2_writeEnable (system_spi_0_io_data_2_writeEnable),
-    .system_spi_0_io_data_2_read        (system_spi_0_io_data_2_read),
-    .system_spi_0_io_data_2_write       (system_spi_0_io_data_2_write),
-    .system_spi_0_io_data_3_writeEnable (system_spi_0_io_data_3_writeEnable),
-    .system_spi_0_io_data_3_read        (system_spi_0_io_data_3_read),
-    .system_spi_0_io_data_3_write       (system_spi_0_io_data_3_write),
-    .system_spi_0_io_ss                 (system_spi_0_io_ss),
-    .system_i2c_0_io_sda_writeEnable    (system_i2c_0_io_sda_writeEnable),
-    .system_i2c_0_io_sda_write          (system_i2c_0_io_sda_write),
-    .system_i2c_0_io_sda_read           (system_i2c_0_io_sda_read),
-    .system_i2c_0_io_scl_writeEnable    (system_i2c_0_io_scl_writeEnable),
-    .system_i2c_0_io_scl_write          (system_i2c_0_io_scl_write),
-    .system_i2c_0_io_scl_read           (system_i2c_0_io_scl_read),
-    .axiA_awaddr                        (axiA_awaddr),
-    .axiA_awlen                         (axiA_awlen),
-    .axiA_awsize                        (axiA_awsize),
-    .axiA_awburst                       (axiA_awburst),
-    .axiA_awlock                        (axiA_awlock),
-    .axiA_awcache                       (axiA_awcache),
-    .axiA_awprot                        (axiA_awprot),
-    .axiA_awqos                         (axiA_awqos),
-    .axiA_awregion                      (axiA_awregion),
-    .axiA_awvalid                       (axiA_awvalid),
-    .axiA_awready                       (axiA_awready),
-    .axiA_wdata                         (axiA_wdata),
-    .axiA_wstrb                         (axiA_wstrb),
-    .axiA_wvalid                        (axiA_wvalid),
-    .axiA_wlast                         (axiA_wlast),
-    .axiA_wready                        (axiA_wready),
-    .axiA_bresp                         (axiA_bresp),
-    .axiA_bvalid                        (axiA_bvalid),
-    .axiA_bready                        (axiA_bready),
-    .axiA_araddr                        (axiA_araddr),
-    .axiA_arlen                         (axiA_arlen),
-    .axiA_arsize                        (axiA_arsize),
-    .axiA_arburst                       (axiA_arburst),
-    .axiA_arlock                        (axiA_arlock),
-    .axiA_arcache                       (axiA_arcache),
-    .axiA_arprot                        (axiA_arprot),
-    .axiA_arqos                         (axiA_arqos),
-    .axiA_arregion                      (axiA_arregion),
-    .axiA_arvalid                       (axiA_arvalid),
-    .axiA_arready                       (axiA_arready),
-    .axiA_rdata                         (axiA_rdata),
-    .axiA_rresp                         (axiA_rresp),
-    .axiA_rlast                         (axiA_rlast),
-    .axiA_rvalid                        (axiA_rvalid),
-    .axiA_rready                        (axiA_rready),
-    .axiAInterrupt                      (axiAInterrupt),
-    .cfg_done                           (cfg_done),
-    .cfg_start                          (cfg_start),
-    .cfg_sel                            (cfg_sel),
-    .cfg_reset                          (cfg_reset),
-    .io_peripheralClk                   (io_peripheralClk),
-    .io_peripheralReset                 (io_peripheralReset),
-    .io_asyncReset                      (io_asyncReset),
-    .io_gpio_sw_n                       (io_gpio_sw_n),
-    .pll_peripheral_locked              (pll_peripheral_locked),
-    .pll_system_locked                  (pll_system_locked),
-    .pll_tse_locked                     (pll_tse_locked),
-    .sd_base_clk                        (sd_base_clk), 
-    .sd_clk_hi                          (sd_clk_hi),
-    .sd_clk_lo                          (sd_clk_lo),
-    .sd_cmd_i                           (sd_cmd_i),
-    .sd_cmd_o                           (sd_cmd_o),
-    .sd_cmd_oe                          (sd_cmd_oe),
-    .sd_dat_i                           (sd_dat_i),
-    .sd_dat_o                           (sd_dat_o),
-    .sd_dat_oe                          (sd_dat_oe),
-    .sd_cd_n                            (sd_cd_n), 
-    .sd_wp                              (sd_wp),
-    .io_tseClk                          (io_tseClk),
-    .rgmii_txd_HI                       (rgmii_txd_HI),
-    .rgmii_txd_LO                       (rgmii_txd_LO),
-    .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI),
-    .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO),
-    .rgmii_txc_HI                       (rgmii_txc_HI),
-    .rgmii_txc_LO                       (rgmii_txc_LO),
-    .rgmii_rxd_HI                       (rgmii_rxd_HI),
-    .rgmii_rxd_LO                       (rgmii_rxd_LO),
-    .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI),
-    .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO),
-    .mux_clk                            (mux_clk),
-    .mux_clk_sw                         (mux_clk_sw),
-    .phy_rst                            (phy_rst),
-    .phy_mdi                            (phy_mdi),
-    .phy_mdo                            (phy_mdo),
-    .phy_mdo_en                         (phy_mdo_en),
-    .phy_mdc                            (phy_mdc),
-    .rgmii_rxc                          (rgmii_rxc),
-    .rgmii_rxc_slow                     (rgmii_rxc_slow)
-);
-
-endmodule

src/sources.list

@@ -1,11 +1,11 @@
-regs/verilog6502_io_regs_pkg.sv
-regs/verilog6502_io_regs.sv
-verilog6502_addr_decoder.sv
-verilog6502_internal_memory.sv
-verilog6502_apb_adapter.sv
-verilog6502_external_memory.sv
-verilog6502_wrapper.sv
+embedded_wrapper/regs/verilog6502_io_regs_pkg.sv
+embedded_wrapper/regs/verilog6502_io_regs.sv
+embedded_wrapper/verilog6502_addr_decoder.sv
+embedded_wrapper/verilog6502_internal_memory.sv
+embedded_wrapper/verilog6502_apb_adapter.sv
+embedded_wrapper/verilog6502_external_memory.sv
+embedded_wrapper/verilog6502_embedded_wrapper.sv
 
 
-ALU.v
-cpu_65c02.v
+original_core/ALU.v
+original_core/cpu_65c02.v