Get it working more

sim/application_wrapper/cache/application_wrapper_cache_arrays_test.py

@@ -0,0 +1,205 @@
+import cocotb
+from cocotb.handle import LogicArray
+
+from cocotb.clock import Clock
+from cocotb.triggers import ReadOnly, NextTimeStep, RisingEdge
+
+import logging
+
+import random
+
+
+logger = logging.getLogger()
+
+logger.setLevel(logging.INFO)
+
+CLK_PERIOD = 5
+
+
+SETS = 64
+WAYS = 4
+
+data_arrays = [{}, {}, {}, {}]
+meta_arrays = [{}, {}, {}, {}]
+
+@cocotb.test
+async def test_sanity(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+
+    await RisingEdge(dut.i_clk)
+    await RisingEdge(dut.i_clk)
+
+
+    for index in range(SETS):
+        for way in range(WAYS):
+            data = random.randbytes(64)
+            meta = random.randint(0, 2**22-1)
+
+            data_arrays[way][index] = data
+            meta_arrays[way][index] = meta
+
+            dut.i_cpu_write_data.value = LogicArray.from_bytes(data, byteorder="little")
+            dut.i_cpu_write_meta.value = meta
+            dut.i_cpu_write_index.value = index
+            dut.i_cpu_write_valid.value = 1 << way
+
+            await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_write_valid.value = 0
+
+    await RisingEdge(dut.i_clk)
+
+    for index in range(SETS):
+        dut.i_cpu_read_index.value = index
+        dut.i_cpu_read_valid.value = 1
+
+        await RisingEdge(dut.i_clk)
+        await ReadOnly()
+
+        raw_data = dut.o_cpu_read_data.value
+        raw_meta = dut.o_cpu_read_meta.value
+
+        meta = [int(m) for m in raw_meta]
+        data_bytes = [v.to_bytes(byteorder="little") for v in raw_data]
+
+        expected_data = [data_arrays[way][index] for way in range(WAYS)]
+        expected_meta = [meta_arrays[way][index] for way in range(WAYS)]
+
+        if data_bytes != expected_data:
+            logger.info("Data Error")
+
+        if meta != expected_meta:
+            logger.info("Meta Error")
+            
+        await NextTimeStep()
+
+    dut.i_cpu_read_valid.value = 0
+
+    for index in range(SETS):
+        for way in range(WAYS):
+            data = random.randbytes(64)
+            meta = random.randint(0, 2**22-1)
+
+            data_arrays[way][index] = data
+            meta_arrays[way][index] = meta
+
+            dut.i_snoop_write_data.value = LogicArray.from_bytes(data, byteorder="little")
+            dut.i_snoop_write_meta.value = meta
+            dut.i_snoop_write_index.value = index
+            dut.i_snoop_write_valid.value = 1 << way
+
+            await RisingEdge(dut.i_clk)
+
+    dut.i_snoop_write_valid.value = 0
+
+    await RisingEdge(dut.i_clk)
+
+    for index in range(SETS):
+        dut.i_snoop_read_index.value = index
+        dut.i_snoop_read_valid.value = 1
+
+        await RisingEdge(dut.i_clk)
+        await ReadOnly()
+
+        raw_data = dut.o_snoop_read_data.value
+        raw_meta = dut.o_snoop_read_meta.value
+
+        meta = [int(m) for m in raw_meta]
+        data_bytes = [v.to_bytes(byteorder="little") for v in raw_data]
+
+        expected_data = [data_arrays[way][index] for way in range(WAYS)]
+        expected_meta = [meta_arrays[way][index] for way in range(WAYS)]
+
+        if data_bytes != expected_data:
+            logger.info("Data Error")
+
+        if meta != expected_meta:
+            logger.info("Meta Error")
+            
+        await NextTimeStep()
+
+    dut.i_snoop_read_valid.value = 0
+
+
+@cocotb.test
+async def test_random_access(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+
+    ITERS = 1024
+
+    for _ in range(ITERS):
+        cpu_write_way = random.randint(0, WAYS-1)
+        cpu_write_set = random.randint(0, SETS-1)
+
+        while True:
+            snoop_write_way = random.randint(0, WAYS-1)
+            snoop_write_set = random.randint(0, SETS-1)
+            if snoop_write_way != cpu_write_way and snoop_write_set != cpu_write_set:
+                break
+
+
+        cpu_write_data = random.randbytes(64)
+        cpu_write_meta = random.randint(0, 2**22-1)
+
+        snoop_write_data = random.randbytes(64)
+        snoop_write_meta = random.randint(0, 2**22-1)
+
+        data_arrays[cpu_write_way][cpu_write_set] = cpu_write_data
+        meta_arrays[cpu_write_way][cpu_write_set] = cpu_write_meta
+
+        data_arrays[snoop_write_way][snoop_write_set] = snoop_write_data
+        meta_arrays[snoop_write_way][snoop_write_set] = snoop_write_meta
+
+        dut.i_cpu_write_data.value = LogicArray.from_bytes(cpu_write_data, byteorder="little")
+        dut.i_cpu_write_meta.value = cpu_write_meta
+        dut.i_cpu_write_index.value = cpu_write_set
+        dut.i_cpu_write_valid.value = 1 << cpu_write_way
+
+        dut.i_snoop_write_data.value = LogicArray.from_bytes(snoop_write_data, byteorder="little")
+        dut.i_snoop_write_meta.value = snoop_write_meta
+        dut.i_snoop_write_index.value = snoop_write_set
+        dut.i_snoop_write_valid.value = 1 << snoop_write_way
+
+
+
+        cpu_read_way = random.randint(0, WAYS-1)
+        cpu_read_set = random.randint(0, SETS-1)
+
+        snoop_read_way = random.randint(0, WAYS-1)
+        snoop_read_set = random.randint(0, SETS-1)
+
+        dut.i_cpu_read_index.value = cpu_read_set
+        dut.i_snoop_read_index.value = snoop_read_set
+
+
+        dut.i_cpu_read_valid.value = 1
+        dut.i_snoop_read_valid.value = 1
+
+        await RisingEdge(dut.i_clk)
+        await ReadOnly()
+
+        cpu_data = dut.o_cpu_read_data.value[cpu_read_way].to_bytes(byteorder="little")
+        cpu_meta = int(dut.o_cpu_read_meta.value[cpu_read_way])
+
+        snoop_data = dut.o_snoop_read_data.value[snoop_read_way].to_bytes(byteorder="little")
+        snoop_meta = int(dut.o_snoop_read_meta.value[snoop_read_way])
+
+        cpu_expected_data = data_arrays[cpu_read_way][cpu_read_set]
+        cpu_expected_meta = meta_arrays[cpu_read_way][cpu_read_set]
+
+        snoop_expected_data = data_arrays[snoop_read_way][snoop_read_set]
+        snoop_expected_meta = meta_arrays[snoop_read_way][snoop_read_set]
+
+        if cpu_data != cpu_expected_data:
+            logger.error("CPU Data Error")
+
+        if cpu_meta != cpu_expected_meta:
+            logger.info("CPU Meta Error")
+
+        if snoop_data != snoop_expected_data:
+            logger.error("snoop Data Error")
+
+        if snoop_meta != snoop_expected_meta:
+            logger.info("snoop Meta Error")
+
+        await NextTimeStep()

sim/application_wrapper/cache/application_wrapper_cache_l1_test.py

@@ -0,0 +1,493 @@
+import cocotb
+from cocotb.handle import Immediate, LogicArray
+
+from cocotb.simulator import get_sim_time
+
+from cocotb.clock import Clock
+from cocotb.triggers import Timer, RisingEdge, FallingEdge, with_timeout
+
+from enum import IntEnum
+
+from collections import defaultdict
+from collections.abc import Mapping
+
+import logging
+
+import random
+
+
+logger = logging.getLogger()
+
+logger.setLevel(logging.INFO)
+
+CLK_PERIOD = 5
+
+reference_cache_data = defaultdict(bytearray)
+
+higher_cache_data = defaultdict(bytearray)
+
+async def cpu_sequencer(dut, sequence: Mapping[int, int, bool, bool]):
+
+
+    addr, do, we, sync = sequence[0]
+
+    dut.i_addr.value = addr
+    dut.i_data.value = do
+    dut.i_we.value = we
+    dut.i_sync.value = sync
+
+    await FallingEdge(dut.i_rst)
+
+    index = 1
+
+    while index < len(sequence):
+        await RisingEdge(dut.i_clk)
+        if not dut.o_rdy.value:
+            continue
+
+        addr, do, we, sync = sequence[index]
+
+        dut.i_addr.value = addr
+        dut.i_data.value = do
+        dut.i_we.value = we
+        dut.i_sync.value = sync
+
+        index += 1
+
+    await Timer(150, "ns")
+
+async def cpu_data_monitor(dut):
+    previous_address = 0
+    address = 0
+
+    we = 0
+    previous_we = 0
+
+    i_data = 0
+    previous_i_data = 0
+
+    await FallingEdge(dut.i_rst)
+
+    while True:
+        await RisingEdge(dut.i_clk)
+        if not dut.o_rdy.value:
+            continue
+
+        previous_address = address
+        previous_we = we
+        address = int(dut.i_addr.value)
+        we = int(dut.i_we.value)
+
+        previous_i_data = i_data
+        i_data = int(dut.i_data.value)
+
+        data = int(dut.o_data.value)
+    
+        if previous_address == 0:
+            continue
+
+        # don't care if it was a write
+        if previous_we:
+
+            index = (previous_address // 64) % 64
+            offset = previous_address % 64
+
+            cacheline = reference_cache_data[index]
+
+            cacheline[offset] = previous_i_data
+            logger.debug(f"We saw a write here {index=} {offset=} previous_data={previous_i_data:x}")
+        else:
+            index = (previous_address // 64) % 64
+            offset = previous_address % 64
+
+            cacheline = reference_cache_data[index]
+
+            expected_data = cacheline[offset]
+
+            if (data != expected_data):
+                logger.error(f"{get_sim_time()} {address=:x} {previous_address=:x} {data=:x} {expected_data=:x}")
+                
+
+
+async def mmu_sequencer(dut):
+    while True:
+        await RisingEdge(dut.i_clk)
+        dut.i_phys_address.value = dut.i_addr.value
+
+async def handle_higher_level_cache(dut):
+    dut.i_cache_rdy.value = 0
+
+    class CacheCmd(IntEnum):
+        CACHE_NONE = 0
+        CACHE_READ = 1
+        CACHE_WRITE = 2
+
+    while True:
+        await RisingEdge(dut.i_clk)
+        dut.i_cache_rdy.value = 0
+
+        if not dut.o_cache_valid.value:
+            continue
+
+        cmd = CacheCmd(dut.o_cache_cmd.value)
+        addr = int(dut.o_cache_addr.value)
+
+        logger.debug(f"{cmd=} {addr=}")
+
+
+        if cmd == CacheCmd.CACHE_READ:
+
+            if addr not in higher_cache_data:
+                data = bytearray(random.randbytes(64))
+                higher_cache_data[addr] = data
+
+            dut.i_cache_data.value = LogicArray.from_bytes(higher_cache_data[addr] , byteorder="little")
+
+            dut.i_cache_rdy.value = 1
+
+            reference_cache_data[int(dut.read_index.value)] = higher_cache_data[addr]
+
+            await RisingEdge(dut.i_clk)
+
+            dut.i_cache_rdy.value = 0
+
+        elif cmd == CacheCmd.CACHE_WRITE:
+
+            dut.i_cache_rdy.value = 1
+
+            data = dut.o_cache_data.value.to_bytes(byteorder="little")
+
+            higher_cache_data[addr] = bytearray(data)
+
+            await RisingEdge(dut.i_clk)
+
+            dut.i_cache_rdy.value = 0
+
+@cocotb.test
+async def sanity_test(dut):
+    expected_cache_misses = 0
+    expected_evictions = 0
+
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    cpu_sequence = [
+        (0x100, 0xaa, True, False),
+        (0x101, 0xbb, True, False),
+        (0x100, 0x00, False, False),
+        (0x101, 0x00, False, False),
+        (0x200, 0xcc, True, False),
+        (0x201, 0xdd, True, False),
+        (0x100, 0x00, False, False),
+        (0x101, 0x00, False, False),
+        (0x200, 0x00, False, False),
+        (0x201, 0x00, False, False),
+        (0x100, 0x11, True, False),
+        (0x101, 0x22, True, False),
+        (0x100, 0x00, False, False),
+        (0x200, 0x33, True, False),
+        (0x101, 0x00, False, False),
+        (0x201, 0x44, True, False),
+        (0x100, 0x00, False, False),
+        (0x200, 0x00, False, False),
+        (0x101, 0x00, False, False),
+        (0x201, 0x00, False, False),
+    ]
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+
+    expected_cache_misses = 2
+    expected_evictions = 0
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+
+@cocotb.test
+async def clean_evict_test(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    # Read from one cacheline, then read from an aliased cacheline without writing.
+    # cacheline should be overwritten without evicting
+    cpu_sequence = [
+        (0x100, 0x00, False, False),
+        (0x1100, 0x00, False, False),
+    ]
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+    expected_cache_misses = 2
+    expected_evictions = 0
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+@cocotb.test
+async def dirty_evict_test(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    # Read from one cacheline, then read from an aliased cacheline without writing.
+    # cacheline should be overwritten without evicting
+    cpu_sequence = [
+        (0x100, 0x41, True, False),
+        (0x101, 0x42, True, False),
+        (0x1100, 0x00, False, False),
+        (0x1100, 0xaa, True, False),
+        (0x100, 0x00, False, False)
+    ]
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+    expected_cache_misses = 3
+    expected_evictions = 2
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+
+@cocotb.test
+async def long_write_thrash_test(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    num_lines_read = 2**20//64
+
+    cpu_sequence = [
+        (i*64, i % 256, True, False)
+    for i in range(num_lines_read)]
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+    # The last 64 lines aren't evicted
+    expected_cache_misses = num_lines_read
+    expected_evictions = num_lines_read - 64
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+
+@cocotb.test
+async def long_write_read_thrash_test(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    num_lines_read = 2**20//64
+
+
+    cpu_sequence = [
+        (i*64, i % 256, True, False)
+    for i in range(num_lines_read)]
+
+    cpu_sequence.extend([
+        (i*64, 0, False, False)
+    for i in range(num_lines_read)])
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+    expected_cache_misses = num_lines_read * 2
+    expected_evictions = num_lines_read
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+
+@cocotb.test
+async def long_write_linear_test(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    num_bytes_read = 2**16
+
+    cpu_sequence = [
+        (i, i % 256, True, False)
+    for i in range(num_bytes_read)]
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+    expected_cache_misses = num_bytes_read // 64
+    expected_evictions = num_bytes_read//64 - 64
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+
+@cocotb.test
+async def long_write_read_linear_test(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    num_bytes_read = 2**16
+
+
+    cpu_sequence = [
+        (i, i % 256, True, False)
+    for i in range(num_bytes_read)]
+
+    cpu_sequence.extend([
+        (i, 0, False, False)
+    for i in range(num_bytes_read)])
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+    expected_cache_misses = (num_bytes_read // 64) * 2
+    expected_evictions = num_bytes_read // 64
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+@cocotb.test
+async def short_write_read_linear_test(dut):
+    # What makes this test "short" is that we read 64 cachelines,
+    # so we shouldn't have to make any evictions
+    # TODO add number of evictions and cachlines loaded as performance counteres
+
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    num_bytes_read = 64*64
+
+    cpu_sequence = [
+        (i, i % 256, True, False)
+    for i in range(num_bytes_read)] # 64 bytes times 64 cachelines
+
+    cpu_sequence.extend([
+        (i, i % 256, False, False)
+    for i in range(num_bytes_read)]) # 64 bytes times 64 cachelines
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)
+
+    expected_cache_misses = num_bytes_read//64
+    expected_evictions = num_bytes_read//64 - 64
+
+    dut_evictions = int(dut.eviction_count.value)
+    dut_misses = int(dut.cache_miss_count.value)
+
+    if dut_evictions != expected_evictions:
+        logger.error(f"Eviction count mismatch! Expected {expected_evictions}, saw {dut_evictions}")
+
+    if dut_misses != expected_cache_misses:
+        logger.error(f"Miss count mismatch! Expected {expected_cache_misses}, saw {dut_misses}")
+
+@cocotb.test
+async def random_access_test(dut):
+    # Just fully random accesses
+    # This is also kind of a thrash test since this is not realistic
+
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(mmu_sequencer(dut))
+    cocotb.start_soon(handle_higher_level_cache(dut))
+    cocotb.start_soon(cpu_data_monitor(dut))
+
+    num_bytes_read = 2**18
+
+    cpu_sequence = [
+        (random.randint(0, 2**32), random.randint(0, 255), random.randint(0,1), random.randint(0,1))
+    for _ in range(num_bytes_read)] # 64 bytes times 64 cachelines
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await cpu_sequencer(dut, cpu_sequence)

sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py

@@ -0,0 +1,402 @@
+import cocotb
+from cocotb.handle import LogicArray, Array, Immediate
+
+from cocotb.clock import Clock
+from cocotb.triggers import ReadOnly, NextTimeStep, RisingEdge, Timer
+
+import logging
+
+import random
+
+from enum import IntEnum
+
+
+logger = logging.getLogger()
+
+logger.setLevel(logging.INFO)
+
+CLK_PERIOD = 5
+
+
+SETS = 64
+WAYS = 4
+
+TAG_WIDTH = 20
+
+data_arrays = [{}, {}, {}, {}]
+meta_arrays = [{}, {}, {}, {}]
+
+lru_array = {}
+
+class MesiState(IntEnum):
+    MESI_INVALID = 0
+    MESI_SHARED = 1,
+    MESI_EXCLUSIVE = 2,
+    MESI_MODIFIED = 3,
+
+def write_cacheline(index: int, way: int, data: bytes, mesi_state: MesiState, tag: int):
+    data_arrays[way][index] = data
+    meta_arrays[way][index] = (mesi_state << 20) | tag
+
+async def handle_cache_arrays(dut):
+
+    while True:
+        await RisingEdge(dut.i_clk)
+        if dut.o_write_valid.value:
+            index = int(dut.o_write_index.value)
+            write_enables = [bool(int(dut.o_write_valid.value) & (1 << i)) for i in range(4)]
+            write_data = dut.o_write_data.value.to_bytes(byteorder="little")
+            write_meta = int(dut.o_write_meta.value)
+            logger.debug(f"Write Valid: {index=} {write_enables=} {write_data=} {write_meta=:#x}")
+
+            for data_array, meta_array, write_enable in zip(data_arrays, meta_arrays, write_enables):
+                if write_enable:
+                    data_array[index] = write_data
+                    meta_array[index] = write_meta
+        if dut.o_read_valid.value:
+            index = int(dut.o_read_index.value)
+            logger.debug(f"Read Valid: {index=}")
+
+            read_data = [LogicArray.from_bytes(data[index], byteorder="little") for data in data_arrays]
+            read_meta = [meta[index] for meta in meta_arrays]
+
+            dut.i_read_data.value = read_data
+            dut.i_read_meta.value = read_meta
+
+async def handle_lru_arrays(dut):
+    while True:
+        await RisingEdge(dut.i_clk)
+        if dut.o_lru_write_valid.value:
+            logger.debug("lru write")
+
+            lru_write_index = int(dut.o_lru_write_index.value)
+            lru_write_data = int(dut.o_lru_write_data.value)
+
+            lru_array[lru_write_index] = lru_write_data
+
+        if dut.o_lru_read_valid.value:
+            logger.debug("lru read")
+
+            lru_read_index = int(dut.o_lru_read_index.value)
+
+            dut.i_lru_read_data.value = lru_array[lru_read_index]
+
+
+
+async def handle_writeback(dut):
+    dut.i_writeback_done.value = 0
+
+    while True:
+        await RisingEdge(dut.i_clk)
+        if not dut.o_writeback_valid.value:
+            continue
+
+        logger.info("Writeback valid")
+        await RisingEdge(dut.i_clk)
+        await RisingEdge(dut.i_clk)
+        dut.i_writeback_done.value = 1
+        await RisingEdge(dut.i_clk)
+        dut.i_writeback_done.value = 0
+
+async def handle_bus_interface(dut):
+    dut.i_memory_done.value = 0
+    dut.i_memory_resp.value = 0
+
+    while True:
+        await RisingEdge(dut.i_clk)
+        if not dut.o_memory_valid.value:
+            continue
+
+        logger.debug("Bus Interface Access")
+        await RisingEdge(dut.i_clk)
+        await RisingEdge(dut.i_clk)
+        dut.i_memory_done.value = 1
+        dut.i_memory_resp.value = 2
+        await RisingEdge(dut.i_clk)
+        dut.i_memory_done.value = 0
+        dut.i_memory_resp.value = 0
+
+@cocotb.test
+async def test_sanity(dut):
+    # Request a read from the cache, then request a write to the cache
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+
+    dut.i_cpu_we.value = 0
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    for way in range(WAYS):
+        for index in range(SETS):
+            write_cacheline(index, way, bytes([0] * 64), MesiState.MESI_EXCLUSIVE, 0)
+
+
+    for i in range(32):
+        if not dut.o_rdy.value:
+            continue
+        
+        dut.i_cpu_tag.value = 0
+        dut.i_cpu_index.value = i
+        dut.i_cpu_offset.value = 0
+
+        dut.i_rdy.value = 1
+
+        dut.i_cpu_we.value = 0
+
+        await RisingEdge(dut.i_clk)
+
+
+@cocotb.test
+async def test_clean_eviction(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_cpu_we.value = 0
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    INDEX = 2
+
+    # Write with tag 0x55
+    for way in range(WAYS):
+        write_cacheline(INDEX, way, bytes([0xaa] * 64), MesiState.MESI_SHARED, way+1)
+
+    # read with tag 0xaa
+    dut.i_cpu_tag.value = 0x0
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 2
+
+    dut.i_rdy.value = 1
+
+    dut.i_cpu_we.value = 0
+
+    await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_tag.value = 0xaa
+
+    await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_tag.value = 0
+
+    await Timer(1, "us")
+
+@cocotb.test
+async def test_eviction(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_cpu_we.value = 0
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    INDEX = 2
+
+    # Write with tag 0x55
+    for way in range(WAYS):
+        write_cacheline(INDEX, way, bytes([0xaa] * 64), MesiState.MESI_MODIFIED, way+1)
+
+    # read with tag 0xaa
+    dut.i_cpu_tag.value = 0x0
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 2
+
+    dut.i_rdy.value = 1
+
+    dut.i_cpu_we.value = 0
+
+    await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_tag.value = 0xaa
+
+    await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_tag.value = 0
+
+    await Timer(1, "us")
+
+@cocotb.test
+async def test_request_ownership(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_cpu_we.value = 0
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    INDEX = 2
+
+    # Write with tag way + 1
+    for way in range(WAYS):
+        write_cacheline(INDEX, way, bytes([0xaa] * 64), MesiState.MESI_SHARED, way+1)
+
+    # write with tag 0x2
+    dut.i_cpu_tag.value = 0
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 2
+    dut.i_cpu_data.value = 0xaa
+
+    dut.i_rdy.value = 1
+
+    dut.i_cpu_we.value = 1
+
+    await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_data.value = 0
+    dut.i_cpu_tag.value = 2
+
+    await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_tag.value = 0
+
+    await Timer(1, "us")
+
+@cocotb.test
+async def test_way_read_thrash(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_cpu_we.value = 0
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    for tag in range(32):
+        dut.i_cpu_tag.value = tag
+        dut.i_cpu_index.value = 0
+        dut.i_cpu_offset.value = 0
+        dut.i_rdy.value = 1
+        await RisingEdge(dut.i_clk)
+        while not dut.o_rdy.value:
+            await RisingEdge(dut.i_clk)
+
+    await Timer(1, "us")
+
+
+@cocotb.test
+async def test_write_waw(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    INDEX = 7
+    TAG = 0xabcd
+
+
+    # unused tag
+    dut.i_cpu_tag.value = 0xffff
+    dut.i_rdy.value = 1
+
+    dut.i_cpu_we.value = 1
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 1
+    dut.i_cpu_data.value = 0xaa
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 1
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 2
+    dut.i_cpu_data.value = 0x55
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 0
+
+    await Timer(1, "us")
+
+@cocotb.test
+async def test_write_raw(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    INDEX = 7
+    TAG = 0xabcd
+
+
+    # unused tag
+    dut.i_cpu_tag.value = 0xffff
+    dut.i_rdy.value = 1
+
+    dut.i_cpu_we.value = 1
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 1
+    dut.i_cpu_data.value = 0x41
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 0
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 1
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 0
+
+    await Timer(1, "us")

sim/application_wrapper/cache/cache.yaml

@@ -0,0 +1,13 @@
+tests:
+  - name: "application_wrapper_cache_arrays_test"
+    toplevel: "application_wrapper_cache_arrays"
+    modules:
+      - "application_wrapper_cache_arrays_test"
+    sources: "sources.list"
+    waves: True
+  - name: "application_wrapper_cache_miss_handler_test"
+    toplevel: "application_wrapper_cache_miss_handler"
+    modules:
+      - "application_wrapper_cache_miss_handler_test"
+    sources: "sources.list"
+    waves: True

sim/application_wrapper/cache/sources.list

@@ -0,0 +1 @@
+../../../src/application_wrapper/sources.list

sim/embedded_wrapper/verilog6502_32bit.yaml

@@ -3,7 +3,7 @@ tests:
     toplevel: "cpu_65c02"
     modules:
       - "verilog6502_32bit_test"
-    sources: "sources.list"
+    sources: "../sources.list"
     waves: True
     defines:
       SIM: "hi"

sim/embedded_wrapper/verilog6502_32bit_asm.yaml

@@ -3,7 +3,7 @@ tests:
     toplevel: "cpu_65c02"
     modules:
       - "verilog6502_32bit_asm_test"
-    sources: "sources.list"
+    sources: "../sources.list"
     waves: True
     defines:
       SIM: "hi"

sim/embedded_wrapper/verilog6502_wrapper.yaml

@@ -3,7 +3,7 @@ tests:
     toplevel: "verilog6502_wrapper_tb"
     modules:
       - "verilog6502_wrapper_test"
-    sources: "sources.list"
+    sources: "../sources.list"
     waves: True
     defines:
       SIM: "hi"

sim/embedded_wrapper/verilog6502_wrapper_tb.sv

@@ -14,7 +14,7 @@ logic i_irq_ext;
 logic i_nmi_ext;
 
 
-verilog6502_wrapper u_dut(
+verilog6502_embedded_wrapper u_dut(
     .clk(clk),
     .rst(rst),
     .s_apb(s_apb),

sim/sources.list

@@ -1,5 +1,5 @@
 verilator.vlt
-verilog6502_wrapper_tb.sv
+embedded_wrapper/verilog6502_wrapper_tb.sv
 
 ../src/sources.list
 

src/application_wrapper/application_wrapper_top.sv

@@ -0,0 +1,3 @@
+module application_wrapper_top();
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_arrays.sv

@@ -0,0 +1,72 @@
+module application_wrapper_cache_arrays #(
+    parameter NUM_WAYS = 4,
+    parameter NUM_SETS = 64,
+
+    localparam DATA_W = 64*8,
+    localparam OFFSET_W = 6,
+    localparam INDEX_W = $clog2(NUM_SETS),
+    localparam TAG_W = 32 - INDEX_W - OFFSET_W,
+
+    localparam META_W = TAG_W + 2
+) (
+    input  logic                i_clk,
+
+    input  logic [INDEX_W-1:0]  i_cpu_read_index,
+    input  logic                i_cpu_read_valid,
+
+    output logic [DATA_W-1:0]   o_cpu_read_data [NUM_WAYS],
+    output logic [META_W-1:0]   o_cpu_read_meta [NUM_WAYS],
+
+    input  logic [INDEX_W-1:0]  i_cpu_write_index,
+    input  logic [NUM_WAYS-1:0] i_cpu_write_valid,
+
+    input  logic [DATA_W-1:0]   i_cpu_write_data,
+    input  logic [META_W-1:0]   i_cpu_write_meta,
+
+    input  logic [INDEX_W-1:0]  i_snoop_read_index,
+    input  logic                i_snoop_read_valid,
+
+    output logic [DATA_W-1:0]   o_snoop_read_data [NUM_WAYS],
+    output logic [META_W-1:0]   o_snoop_read_meta [NUM_WAYS],
+
+    input  logic [INDEX_W-1:0]  i_snoop_write_index,
+    input  logic [NUM_WAYS-1:0] i_snoop_write_valid,
+
+    input  logic [DATA_W-1:0]   i_snoop_write_data,
+    input  logic [META_W-1:0]   i_snoop_write_meta
+);
+
+
+// memory arrays. 
+// In order to make these WRITE_FIRST, we put a blocking assignment
+// for the write data before the assignment to the read data
+
+logic [DATA_W-1:0] data_arrays [NUM_SETS][NUM_WAYS];
+logic [META_W-1:0] meta_arrays [NUM_SETS][NUM_WAYS];
+
+
+always @(posedge i_clk) begin
+    for (int i = 0; i < NUM_WAYS; i++) begin
+        if (i_cpu_write_valid[i]) begin
+            data_arrays[i_cpu_write_index][i] = i_cpu_write_data;
+            meta_arrays[i_cpu_write_index][i] = i_cpu_write_meta;
+        end
+
+        if (i_snoop_write_valid[i]) begin
+            data_arrays[i_snoop_write_index][i] = i_snoop_write_data;
+            meta_arrays[i_snoop_write_index][i] = i_snoop_write_meta;
+        end
+    end
+    
+    if (i_cpu_read_valid) begin
+        o_cpu_read_data = data_arrays[i_cpu_read_index];
+        o_cpu_read_meta = meta_arrays[i_cpu_read_index];
+    end
+
+    if (i_snoop_read_valid) begin
+        o_snoop_read_data = data_arrays[i_snoop_read_index];
+        o_snoop_read_meta = meta_arrays[i_snoop_read_index];
+    end
+end
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_miss_handler.sv

@@ -0,0 +1,477 @@
+import application_wrapper_cache_pkg::*;
+
+module application_wrapper_cache_miss_handler #(
+    parameter NUM_WAYS = 4,
+    parameter NUM_SETS = 64,
+    
+    localparam CPU_W = 8,
+    localparam DATA_W = 64*8,
+    localparam OFFSET_W = 6,
+    localparam INDEX_W = $clog2(NUM_SETS),
+    localparam TAG_W = 32 - INDEX_W - OFFSET_W,
+    localparam LRU_W = NUM_WAYS-1,
+
+    localparam META_W = TAG_W + 2
+) (
+    input  logic                i_clk,
+    input  logic                i_rst,
+
+    // NOTE: tag is physical tag, expected 1 cycle after the index and the offset
+    input  logic [TAG_W-1:0]    i_cpu_tag,
+    input  logic [INDEX_W-1:0]  i_cpu_index,
+    input  logic [OFFSET_W-1:0] i_cpu_offset,
+
+    input  logic                i_rdy,
+    output logic                o_rdy,
+
+    input  logic                i_cpu_we,
+
+    input  logic [CPU_W-1:0]    i_cpu_data,
+    output logic [CPU_W-1:0]    o_cpu_data,
+
+    output logic [INDEX_W-1:0]  o_read_index,
+    output logic                o_read_valid,
+
+    input  logic [DATA_W-1:0]   i_read_data [NUM_WAYS],
+    input  logic [META_W-1:0]   i_read_meta [NUM_WAYS],
+
+    output logic [INDEX_W-1:0]  o_write_index,
+    output logic [NUM_WAYS-1:0] o_write_valid,
+
+    output logic [DATA_W-1:0]   o_write_data,
+    output logic [META_W-1:0]   o_write_meta,
+
+    output logic [INDEX_W-1:0]  o_lru_read_index,
+    output logic                o_lru_read_valid,
+    input  logic [LRU_W-1:0]    i_lru_read_data,
+
+    output logic [INDEX_W-1:0]  o_lru_write_index,
+    output logic                o_lru_write_valid,
+    output logic [LRU_W-1:0]    o_lru_write_data,
+
+    output logic [DATA_W-1:0]   o_writeback_data,
+    output logic [31:0]         o_writeback_addr,
+    output logic                o_writeback_valid,
+    input  logic                i_writeback_done,
+
+    output logic [31:0]         o_memory_addr,
+    output logic                o_memory_valid,
+    output cache_cmd_e          o_memory_cmd,
+
+    input  logic [DATA_W-1:0]   i_memory_data,
+    input  logic                i_memory_done,
+    input  cache_resp_e         i_memory_resp
+);
+
+
+enum logic [3:0] {
+    RESET,
+    CLEAR_MEMORY,
+    IDLE,
+    CHECK_VICTIM,
+    WRITEBACK,
+    WAIT_WRITEBACK_ACK,
+    REQUEST_MEMORY,
+    WAIT_MEMORY,
+    REQUEST_OWNERSHIP
+} state, state_next;
+
+logic [INDEX_W-1:0] clear_index, clear_index_next;
+
+logic cpu_we_d1;
+logic [CPU_W-1:0] cpu_i_data_d1;
+
+logic [TAG_W-1:0] cpu_tag_d1;
+logic [INDEX_W-1:0]  cpu_index_d1, cpu_index_d2;
+logic [OFFSET_W-1:0] cpu_offset_d1, cpu_offset_d2;
+
+logic [TAG_W-1:0] cpu_tag_new, cpu_tag_new_next;
+logic [INDEX_W-1:0] cpu_index_new, cpu_index_new_next;
+logic [OFFSET_W-1:0] cpu_offset_new, cpu_offset_new_next;
+logic [$clog2(NUM_WAYS)-1:0] cpu_way_new, cpu_way_new_next;
+logic [7:0] cpu_data_new, cpu_data_new_next;
+logic cpu_we_new, cpu_we_new_next;
+
+logic previous_was_valid, previous_was_valid_next;
+
+logic way_match_found;
+logic [NUM_WAYS-1:0] way_select_mask;
+logic [$clog2(NUM_WAYS)-1:0] way_select_idx;
+mesi_e mesi;
+logic [TAG_W-1:0] tag;
+
+logic [31:0] read_req_addr, read_req_addr_next;
+
+always_ff @(posedge i_clk) begin
+    if (i_rst) begin
+        state <= RESET;
+    end else begin
+        state <= state_next;
+    end
+
+    previous_was_valid <= previous_was_valid_next;
+
+    read_req_addr <= read_req_addr_next;
+
+    cpu_offset_new <= cpu_offset_new_next;
+    cpu_index_new <= cpu_index_new_next;
+    cpu_tag_new <= cpu_tag_new_next;
+    cpu_way_new <= cpu_way_new_next;
+    cpu_data_new <= cpu_data_new_next;
+    cpu_we_new <= cpu_we_new_next;
+
+    clear_index <= clear_index_next;
+    cpu_we_d1 <= i_cpu_we;
+    cpu_i_data_d1 <= i_cpu_data;
+    cpu_index_d1 <= i_cpu_index;
+    cpu_index_d2 <= cpu_index_d1;
+    cpu_tag_d1 <= i_cpu_tag;
+    cpu_offset_d1 <= i_cpu_offset;
+    cpu_offset_d2 <= cpu_offset_d1;
+end
+
+always_comb begin
+    o_rdy = '0;
+    o_cpu_data = '0;
+
+    o_read_valid = '0;
+    o_read_index = '0;
+
+    o_write_valid = '0;
+    o_write_index = '0;
+    o_write_data = '0;
+    o_write_meta = '0;
+
+    o_lru_read_valid = '0;
+    o_lru_read_index = '0;
+    o_lru_write_valid = '0;
+    o_lru_write_index = '0;
+    o_lru_write_data = '0;
+
+    o_writeback_data = '0;
+    o_writeback_addr = '0;
+    o_writeback_valid = '0;
+
+    o_memory_addr = '0;
+    o_memory_valid = '0;
+    o_memory_cmd = CACHE_CMD_NONE;
+
+    way_match_found = '0;
+    way_select_mask = '0;
+    way_select_idx = '0;
+    mesi = MESI_INVALID;
+    tag = '0;
+
+    cpu_offset_new_next = cpu_offset_new;
+    cpu_index_new_next = cpu_index_new;
+    cpu_tag_new_next = cpu_tag_new;
+    cpu_way_new_next = cpu_way_new;
+    cpu_data_new_next = cpu_data_new;
+    cpu_we_new_next = cpu_we_new;
+
+    read_req_addr_next = read_req_addr;
+
+    clear_index_next = clear_index;
+
+    previous_was_valid_next = previous_was_valid;
+
+    state_next = state;
+
+
+    case (state)
+        RESET: begin
+            state_next = CLEAR_MEMORY;
+            clear_index_next = '0;
+            previous_was_valid_next = '0;
+        end
+
+        CLEAR_MEMORY: begin
+            o_write_valid = '1;
+            o_write_data = '0;
+            o_write_meta = {MESI_INVALID, (TAG_W)'('0)};
+            o_write_index = clear_index;
+
+            o_lru_write_index = clear_index;
+            o_lru_write_data = '0;
+            o_lru_write_valid = '1;
+
+            clear_index_next = clear_index + 1;
+            if (clear_index_next == '0) begin
+                state_next = IDLE;
+            end
+        end
+
+        IDLE: begin
+            // by default, o_rdy is 1 unless something is wrong
+            o_rdy = '1;
+
+            if (previous_was_valid) begin
+                // data from previous cycle that was read from arrays
+                way_match_found = '0;
+                way_select_mask = '0;
+                for (int i = 0; i < NUM_WAYS; i++) begin
+                    {mesi, tag} = i_read_meta[i];
+                    if (tag == i_cpu_tag && mesi != MESI_INVALID) begin
+                        way_match_found = '1;
+                        way_select_mask[i] = '1;
+                        way_select_idx = 2'(i);
+                        break;
+                    end
+                end
+
+                // We have a match, so either read or write data
+                if (way_match_found) begin
+                    if (cpu_we_d1) begin
+                        // write data back to the cache array
+                        // check if we are in the M or E states before we write.
+                        // If we are in S then we need to request ownership before
+                        // we can modify it.
+                        if (mesi == MESI_MODIFIED || mesi == MESI_EXCLUSIVE) begin
+                            o_write_data = i_read_data[way_select_idx];
+                            o_write_data[cpu_offset_d1*8 +: CPU_W] = cpu_i_data_d1;
+                            o_write_meta = {MESI_MODIFIED, i_cpu_tag};
+                            o_write_valid = way_select_mask;
+                            o_write_index = cpu_index_d1;
+
+                        end else begin
+                            o_rdy = '0;
+
+                            o_memory_addr = {i_cpu_tag, cpu_index_d1, (OFFSET_W)'('0)};
+                            o_memory_cmd = CACHE_CMD_CLEAN_UNIQUE;
+                            o_memory_valid = '1;
+
+                            cpu_offset_new_next = cpu_offset_d1;
+                            cpu_index_new_next = cpu_index_d1;
+                            cpu_tag_new_next = i_cpu_tag;
+                            cpu_way_new_next = way_select_idx;
+                            cpu_data_new_next = cpu_i_data_d1;
+
+                            state_next = REQUEST_OWNERSHIP;
+                        end
+                    end else begin
+                        // Send the data to the CPU
+                        o_cpu_data = i_read_data[way_select_idx][cpu_offset_d1*8 +: CPU_W];
+                    end
+
+                    // update lru
+                    // start by copying the read data, then change the bits
+                    // based on what we matched.
+                    o_lru_write_index = cpu_index_d1;
+                    o_lru_write_data = i_lru_read_data;
+                    o_lru_write_valid = '1;
+
+                    case (way_select_mask)
+                        4'b0001: begin
+                            o_lru_write_data[0] = '1;
+                            o_lru_write_data[1] = '1;
+                        end
+
+                        4'b0010: begin
+                            o_lru_write_data[0] = '1;
+                            o_lru_write_data[1] = '0;
+                        end
+
+                        4'b0100: begin
+                            o_lru_write_data[0] = '0;
+                            o_lru_write_data[2] = '1;
+                        end
+
+                        4'b1000: begin
+                            o_lru_write_data[0] = '0;
+                            o_lru_write_data[2] = '0;
+                        end
+
+                        default: begin
+                        end
+                    endcase
+                end else begin
+                    o_rdy = '0;
+                    state_next = CHECK_VICTIM;
+
+                    cpu_data_new_next = cpu_i_data_d1;
+                    cpu_we_new_next = cpu_we_d1;
+                end
+
+            end
+
+            // Read from arrays
+            o_read_index = i_cpu_index;
+            o_read_valid = i_rdy & o_rdy;
+
+            o_lru_read_index = i_cpu_index;
+            o_lru_read_valid = i_rdy & o_rdy;
+
+            previous_was_valid_next = '1;
+        end
+
+        REQUEST_OWNERSHIP: begin
+            if (i_memory_done) begin
+                // write to the cacheline here.
+                o_write_data = i_read_data[cpu_way_new];
+                o_write_data[cpu_offset_new*8 +: CPU_W] = cpu_data_new;
+                o_write_meta = {MESI_MODIFIED, cpu_tag_new};
+                o_write_valid = (1 << cpu_way_new);
+                o_write_index = cpu_index_new;
+                state_next = IDLE;
+
+                // update lru
+                // start by copying the read data, then change the bits
+                // based on what we matched.
+                o_lru_write_index = cpu_index_new;
+                o_lru_write_data = i_lru_read_data;
+                o_lru_write_valid = '1;
+
+                case (1 << cpu_way_new)
+                    4'b0001: begin
+                        o_lru_write_data[0] = '1;
+                        o_lru_write_data[1] = '1;
+                    end
+
+                    4'b0010: begin
+                        o_lru_write_data[0] = '1;
+                        o_lru_write_data[1] = '0;
+                    end
+
+                    4'b0100: begin
+                        o_lru_write_data[0] = '0;
+                        o_lru_write_data[2] = '1;
+                    end
+
+                    4'b1000: begin
+                        o_lru_write_data[0] = '0;
+                        o_lru_write_data[2] = '0;
+                    end
+
+                    default: begin
+                    end
+                endcase
+            end
+        end
+
+        CHECK_VICTIM: begin
+            // first use the LRU, then overwrite if there was an invalid way
+
+            way_select_idx[0] = i_lru_read_data[0];
+            way_select_idx[1] = way_select_idx[0] ? i_lru_read_data[2] : i_lru_read_data[1];
+
+            for (int i = 0; i < NUM_WAYS; i++) begin
+                {mesi, tag} = i_read_meta[i];
+                if (mesi == MESI_INVALID) begin
+                    way_select_idx = 2'(i);
+                    break;
+                end
+            end
+
+            {mesi, tag} = i_read_meta[way_select_idx];
+
+            if (mesi == MESI_MODIFIED) begin
+                o_writeback_data = i_read_data[way_select_idx];
+                o_writeback_addr = {tag, cpu_index_d2, (OFFSET_W)'('0)};
+                o_writeback_valid = '1;
+                state_next = WAIT_WRITEBACK_ACK;
+            end else if (mesi == MESI_EXCLUSIVE || mesi == MESI_SHARED) begin
+                o_memory_addr = {tag, cpu_index_d2, (OFFSET_W)'('0)};
+                o_memory_valid = '1;
+                o_memory_cmd = CACHE_CMD_EVICT;
+                state_next = WAIT_WRITEBACK_ACK;
+            end else begin
+                state_next = REQUEST_MEMORY;
+            end
+
+            read_req_addr_next = {cpu_tag_d1, cpu_index_d2, (OFFSET_W)'('0)};
+            cpu_offset_new_next = cpu_offset_d2;
+            cpu_index_new_next = cpu_index_d2;
+            cpu_tag_new_next = cpu_tag_d1;
+            cpu_way_new_next = way_select_idx;
+        end
+
+        WAIT_WRITEBACK_ACK: begin
+            // This state is also used when sending the EVICT command,
+            // before sending the read.
+            if (i_writeback_done || i_memory_done) begin
+                state_next = REQUEST_MEMORY;
+            end
+        end
+
+        REQUEST_MEMORY: begin
+            // This state can be put into WAIT_WRITEBACK_ACK and CHECK_VICTIM
+            o_memory_addr = read_req_addr;
+            o_memory_valid = '1;
+
+            if (cpu_we_new) begin
+                o_memory_cmd = CACHE_CMD_READ_UNIQUE;
+            end else begin
+                o_memory_cmd = CACHE_CMD_READ;
+            end
+            state_next = WAIT_MEMORY;
+        end
+
+        WAIT_MEMORY: begin
+            if (i_memory_done) begin
+                o_write_valid = (1 << cpu_way_new);
+                o_write_data = i_memory_data;
+                o_write_index = cpu_index_new;
+                if (cpu_we_new) begin
+                    o_write_data[cpu_offset_new*8 +: CPU_W] = cpu_data_new;
+                    o_write_meta = {MESI_MODIFIED, cpu_tag_new};
+                end else begin
+                    if (i_memory_resp == CACHE_RSP_SHARED) begin
+                        o_write_meta = {MESI_SHARED, cpu_tag_new};
+                    end else if (i_memory_resp == CACHE_RSP_EXCLUSIVE) begin
+                        o_write_meta = {MESI_EXCLUSIVE, cpu_tag_new};
+                    end
+                    o_cpu_data = i_memory_data[cpu_offset_new*8 +: CPU_W];
+                end
+
+                o_rdy = '1;
+
+                // update lru
+                // start by copying the read data, then change the bits
+                // based on what we matched.
+                o_lru_write_index = cpu_index_new;
+                o_lru_write_data = i_lru_read_data;
+                o_lru_write_valid = '1;
+
+                case (1 << cpu_way_new)
+                    4'b0001: begin
+                        o_lru_write_data[0] = '1;
+                        o_lru_write_data[1] = '1;
+                    end
+
+                    4'b0010: begin
+                        o_lru_write_data[0] = '1;
+                        o_lru_write_data[1] = '0;
+                    end
+
+                    4'b0100: begin
+                        o_lru_write_data[0] = '0;
+                        o_lru_write_data[2] = '1;
+                    end
+
+                    4'b1000: begin
+                        o_lru_write_data[0] = '0;
+                        o_lru_write_data[2] = '0;
+                    end
+
+                    default: begin
+                    end
+                endcase
+
+                o_read_index = i_cpu_index;
+                o_read_valid = i_rdy & o_rdy;
+
+                o_lru_read_index = i_cpu_index;
+                o_lru_read_valid = i_rdy & o_rdy;
+
+                state_next = IDLE;
+            end
+        end
+
+        default: begin
+            state_next = IDLE;
+        end
+
+    endcase
+end
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_pkg.sv

@@ -0,0 +1,35 @@
+package application_wrapper_cache_pkg;
+
+    typedef struct {
+        logic cache_disable;
+        logic read_eanble;
+        logic write_enable;
+        logic execute_enable;
+        logic supervisor;
+        logic present;
+        logic write_through;
+    } page_table_entry_t;
+
+    typedef enum logic [2:0] {
+        CACHE_CMD_NONE,
+        CACHE_CMD_READ,
+        CACHE_CMD_READ_UNIQUE,
+        CACHE_CMD_WRITE,
+        CACHE_CMD_CLEAN_UNIQUE,
+        CACHE_CMD_EVICT
+    } cache_cmd_e;
+
+    typedef enum logic [1:0] {
+        CACHE_RSP_NONE,
+        CACHE_RSP_SHARED,
+        CACHE_RSP_EXCLUSIVE
+    } cache_resp_e;
+
+    typedef enum logic [1:0] {
+        MESI_INVALID,
+        MESI_SHARED,
+        MESI_EXCLUSIVE,
+        MESI_MODIFIED
+    } mesi_e;
+
+endpackage

src/application_wrapper/cache/application_wrapper_mmu.sv

@@ -0,0 +1,21 @@
+import application_wrapper_cache_pkg::*;
+
+module application_wrapper_mmu #(
+    parameter TLB_COUNT = 32,
+    parameter ADDR_WIDTH = 32,
+    parameter LOG2_PAGE_SIZE = 12
+) (
+    input  logic                    i_clk,
+    input  logic                    i_rst,
+
+    input  logic [ADDR_WIDTH-1:0]   i_cpu_addr,
+    input                           i_we,
+    input                           i_rdy,
+    input                           o_rdy,
+
+    output logic [ADDR_WIDTH-1:0]   o_phys_address,
+    output page_table_entry_t       o_table_entry,
+    output logic                    o_mmu_valid
+);
+
+endmodule

src/application_wrapper/sources.list

@@ -0,0 +1,7 @@
+cache/application_wrapper_cache_pkg.sv
+cache/application_wrapper_cache_arrays.sv
+cache/application_wrapper_cache_miss_handler.sv
+cache/application_wrapper_mmu.sv
+cache/application_wrapper_cache_top.sv
+
+application_wrapper_top.sv

src/embedded_wrapper/verilog6502_embedded_wrapper.sv

@@ -7,7 +7,7 @@
 // 0x00010000-0xFFFFEFFF    External AXI
 // 0xFFFFF000-0xFFFFFFFF    Processor IO 
 
-module verilog6502_wrapper(
+module verilog6502_embedded_wrapper(
     input   clk,
     input   rst,
 

src/fpga6502.sv

@@ -1,387 +0,0 @@
-module fpga6502 (
-    output		    jtagCtrl_tdi,
-    input		    jtagCtrl_tdo,
-    output		    jtagCtrl_enable,
-    output		    jtagCtrl_capture,
-    output		    jtagCtrl_shift,
-    output		    jtagCtrl_update,
-    output		    jtagCtrl_reset,
-    input		    ut_jtagCtrl_tdi,
-    output		    ut_jtagCtrl_tdo,
-    input		    ut_jtagCtrl_enable,
-    input		    ut_jtagCtrl_capture,
-    input		    ut_jtagCtrl_shift,
-    input		    ut_jtagCtrl_update,
-    input		    ut_jtagCtrl_reset,
-    input		    io_cfuClk,
-    input		    io_cfuReset,
-    input		    cpu0_customInstruction_cmd_valid,
-    output		    cpu0_customInstruction_cmd_ready,
-    input [9:0]     cpu0_customInstruction_function_id,
-    input [31:0]    cpu0_customInstruction_inputs_0,
-    input [31:0]    cpu0_customInstruction_inputs_1,
-    output		    cpu0_customInstruction_rsp_valid,
-    input		    cpu0_customInstruction_rsp_ready,
-    output [31:0]   cpu0_customInstruction_outputs_0,
-    input		    cpu1_customInstruction_cmd_valid,
-    output		    cpu1_customInstruction_cmd_ready,
-    input [9:0]     cpu1_customInstruction_function_id,
-    input [31:0]    cpu1_customInstruction_inputs_0,
-    input [31:0]    cpu1_customInstruction_inputs_1,
-    output		    cpu1_customInstruction_rsp_valid,
-    input		    cpu1_customInstruction_rsp_ready,
-    output [31:0]   cpu1_customInstruction_outputs_0,
-    input		    cpu2_customInstruction_cmd_valid,
-    output		    cpu2_customInstruction_cmd_ready,
-    input [9:0]     cpu2_customInstruction_function_id,
-    input [31:0]    cpu2_customInstruction_inputs_0,
-    input [31:0]    cpu2_customInstruction_inputs_1,
-    output		    cpu2_customInstruction_rsp_valid,
-    input		    cpu2_customInstruction_rsp_ready,
-    output [31:0]   cpu2_customInstruction_outputs_0,
-    input		    cpu3_customInstruction_cmd_valid,
-    output		    cpu3_customInstruction_cmd_ready,
-    input [9:0]     cpu3_customInstruction_function_id,
-    input [31:0]    cpu3_customInstruction_inputs_0,
-    input [31:0]    cpu3_customInstruction_inputs_1,
-    output		    cpu3_customInstruction_rsp_valid,
-    input		    cpu3_customInstruction_rsp_ready,
-    output [31:0]   cpu3_customInstruction_outputs_0,
-    output		    io_ddrMasters_0_aw_valid,
-    input		    io_ddrMasters_0_aw_ready,
-    output [31:0]   io_ddrMasters_0_aw_payload_addr,
-    output [3:0]    io_ddrMasters_0_aw_payload_id,
-    output [3:0]    io_ddrMasters_0_aw_payload_region,
-    output [7:0]    io_ddrMasters_0_aw_payload_len,
-    output [2:0]    io_ddrMasters_0_aw_payload_size,
-    output [1:0]    io_ddrMasters_0_aw_payload_burst,
-    output		    io_ddrMasters_0_aw_payload_lock,
-    output [3:0]    io_ddrMasters_0_aw_payload_cache,
-    output [3:0]    io_ddrMasters_0_aw_payload_qos,
-    output [2:0]    io_ddrMasters_0_aw_payload_prot,
-    output		    io_ddrMasters_0_aw_payload_allStrb,
-    output		    io_ddrMasters_0_w_valid,
-    input		    io_ddrMasters_0_w_ready,
-    output [127:0]  io_ddrMasters_0_w_payload_data,
-    output [15:0]   io_ddrMasters_0_w_payload_strb,
-    output		    io_ddrMasters_0_w_payload_last,
-    input		    io_ddrMasters_0_b_valid,
-    output		    io_ddrMasters_0_b_ready,
-    input [3:0]     io_ddrMasters_0_b_payload_id,
-    input [1:0]     io_ddrMasters_0_b_payload_resp,
-    output		    io_ddrMasters_0_ar_valid,
-    input		    io_ddrMasters_0_ar_ready,
-    output [31:0]   io_ddrMasters_0_ar_payload_addr,
-    output [3:0]    io_ddrMasters_0_ar_payload_id,
-    output [3:0]    io_ddrMasters_0_ar_payload_region,
-    output [7:0]    io_ddrMasters_0_ar_payload_len,
-    output [2:0]    io_ddrMasters_0_ar_payload_size,
-    output [1:0]    io_ddrMasters_0_ar_payload_burst,
-    output		    io_ddrMasters_0_ar_payload_lock,
-    output [3:0]    io_ddrMasters_0_ar_payload_cache,
-    output [3:0]    io_ddrMasters_0_ar_payload_qos,
-    output [2:0]    io_ddrMasters_0_ar_payload_prot,
-    input		    io_ddrMasters_0_r_valid,
-    output		    io_ddrMasters_0_r_ready,
-    input [127:0]   io_ddrMasters_0_r_payload_data,
-    input [3:0]     io_ddrMasters_0_r_payload_id,
-    input [1:0]     io_ddrMasters_0_r_payload_resp,
-    input		    io_ddrMasters_0_r_payload_last,
-    input		    io_ddrMasters_0_clk,
-    input		    io_ddrMasters_0_reset,
-    output          io_ddrMasters_memCheck_pass,
-    output		    userInterruptA,
-    output		    userInterruptB,
-    output		    userInterruptC,
-    output		    userInterruptD,
-    output		    userInterruptE,
-    output		    userInterruptF,
-    output		    userInterruptH,
-    output		    userInterruptG,
-    output          userInterruptI,
-    input [3:0]     system_gpio_0_io_read,
-    output [3:0]    system_gpio_0_io_write,
-    output [3:0]    system_gpio_0_io_writeEnable,
-    output		    system_uart_0_io_txd,
-    input		    system_uart_0_io_rxd,
-    output		    system_spi_0_io_sclk_write,
-    output		    system_spi_0_io_data_0_writeEnable,
-    input		    system_spi_0_io_data_0_read,
-    output		    system_spi_0_io_data_0_write,
-    output		    system_spi_0_io_data_1_writeEnable,
-    input		    system_spi_0_io_data_1_read,
-    output		    system_spi_0_io_data_1_write,
-    output		    system_spi_0_io_data_2_writeEnable,
-    input		    system_spi_0_io_data_2_read,
-    output		    system_spi_0_io_data_2_write,
-    output		    system_spi_0_io_data_3_writeEnable,
-    input		    system_spi_0_io_data_3_read,
-    output		    system_spi_0_io_data_3_write,
-    output [3:0]    system_spi_0_io_ss,
-    output		    system_i2c_0_io_sda_writeEnable,
-    output		    system_i2c_0_io_sda_write,
-    input		    system_i2c_0_io_sda_read,
-    output		    system_i2c_0_io_scl_writeEnable,
-    output		    system_i2c_0_io_scl_write,
-    input		    system_i2c_0_io_scl_read,
-    input [31:0]    axiA_awaddr,
-    input [7:0]	    axiA_awlen,
-    input [2:0]	    axiA_awsize,
-    input [1:0]	    axiA_awburst,
-    input		    axiA_awlock,
-    input [3:0]	    axiA_awcache,
-    input [2:0]	    axiA_awprot,
-    input [3:0]	    axiA_awqos,
-    input [3:0]	    axiA_awregion,
-    input		    axiA_awvalid,
-    output		    axiA_awready,
-    input [31:0]    axiA_wdata,
-    input [3:0]     axiA_wstrb,
-    input		    axiA_wvalid,
-    input		    axiA_wlast,
-    output		    axiA_wready,
-    output [1:0]    axiA_bresp,
-    output		    axiA_bvalid,
-    input		    axiA_bready,
-    input [31:0]    axiA_araddr,
-    input [7:0]	    axiA_arlen,
-    input [2:0]	    axiA_arsize,
-    input [1:0]	    axiA_arburst,
-    input		    axiA_arlock,
-    input [3:0]	    axiA_arcache,
-    input [2:0]	    axiA_arprot,
-    input [3:0]	    axiA_arqos,
-    input [3:0]	    axiA_arregion,
-    input		    axiA_arvalid,
-    output		    axiA_arready,
-    output [31:0]   axiA_rdata,
-    output [1:0]    axiA_rresp,
-    output		    axiA_rlast,
-    output		    axiA_rvalid,
-    input		    axiA_rready,
-    output          axiAInterrupt,
-    input           cfg_done,
-    output          cfg_start,
-    output          cfg_sel,
-    output          cfg_reset,
-    input		    io_peripheralClk,
-    input           io_peripheralReset,
-    output          io_asyncReset,
-    input           io_gpio_sw_n, 
-    input           pll_peripheral_locked,
-    input           pll_system_locked,
-    input           pll_tse_locked,
-    //  SDHC
-    input           sd_base_clk, 
-    output          sd_clk_hi,
-    output          sd_clk_lo,
-    input           sd_cmd_i,
-    output          sd_cmd_o,
-    output          sd_cmd_oe,
-    input  [3:0]    sd_dat_i,
-    output [3:0]    sd_dat_o,
-    output [3:0]    sd_dat_oe,
-    input           sd_cd_n, 
-    input           sd_wp,
-    // TSEMAC
-    input           io_tseClk,
-    // MAC 
-    output [3:0]    rgmii_txd_HI,
-    output [3:0]    rgmii_txd_LO,
-    output          rgmii_tx_ctl_HI,
-    output          rgmii_tx_ctl_LO,
-    output          rgmii_txc_HI,
-    output          rgmii_txc_LO,
-    input  [3:0]    rgmii_rxd_HI,
-    input  [3:0]    rgmii_rxd_LO,
-    input           rgmii_rx_ctl_HI,
-    input           rgmii_rx_ctl_LO,
-    input           mux_clk,
-    output [1:0]    mux_clk_sw,
-    // PHY
-    output          phy_rst,
-    input           phy_mdi,
-    output          phy_mdo,
-    output          phy_mdo_en,
-    output          phy_mdc,
-    input           rgmii_rxc,      
-    input           rgmii_rxc_slow
-);
-
-
-
-top_soc u_top_soc (
-    .jtagCtrl_tdi       (jtagCtrl_tdi),
-    .jtagCtrl_tdo    (jtagCtrl_tdo),
-    .jtagCtrl_enable (jtagCtrl_enable),
-    .jtagCtrl_capture    (jtagCtrl_capture),
-    .jtagCtrl_shift  (jtagCtrl_shift),
-    .jtagCtrl_update (jtagCtrl_update),
-    .jtagCtrl_reset  (jtagCtrl_reset),
-    .ut_jtagCtrl_tdi (ut_jtagCtrl_tdi),
-    .ut_jtagCtrl_tdo (ut_jtagCtrl_tdo),
-    .ut_jtagCtrl_enable  (ut_jtagCtrl_enable),
-    .ut_jtagCtrl_capture (ut_jtagCtrl_capture),
-    .ut_jtagCtrl_shift   (ut_jtagCtrl_shift),
-    .ut_jtagCtrl_update  (ut_jtagCtrl_update),
-    .ut_jtagCtrl_reset   (ut_jtagCtrl_reset),
-    .io_cfuClk   (io_cfuClk),
-    .io_cfuReset (io_cfuReset),
-    .io_ddrMasters_0_aw_valid           (io_ddrMasters_0_aw_valid),
-    .io_ddrMasters_0_aw_ready           (io_ddrMasters_0_aw_ready),
-    .io_ddrMasters_0_aw_payload_addr    (io_ddrMasters_0_aw_payload_addr),
-    .io_ddrMasters_0_aw_payload_id      (io_ddrMasters_0_aw_payload_id),
-    .io_ddrMasters_0_aw_payload_region  (io_ddrMasters_0_aw_payload_region),
-    .io_ddrMasters_0_aw_payload_len     (io_ddrMasters_0_aw_payload_len),
-    .io_ddrMasters_0_aw_payload_size    (io_ddrMasters_0_aw_payload_size),
-    .io_ddrMasters_0_aw_payload_burst   (io_ddrMasters_0_aw_payload_burst),
-    .io_ddrMasters_0_aw_payload_lock    (io_ddrMasters_0_aw_payload_lock),
-    .io_ddrMasters_0_aw_payload_cache   (io_ddrMasters_0_aw_payload_cache),
-    .io_ddrMasters_0_aw_payload_qos     (io_ddrMasters_0_aw_payload_qos),
-    .io_ddrMasters_0_aw_payload_prot    (io_ddrMasters_0_aw_payload_prot),
-    .io_ddrMasters_0_aw_payload_allStrb (io_ddrMasters_0_aw_payload_allStrb),
-    .io_ddrMasters_0_w_valid            (io_ddrMasters_0_w_valid),
-    .io_ddrMasters_0_w_ready            (io_ddrMasters_0_w_ready),
-    .io_ddrMasters_0_w_payload_data     (io_ddrMasters_0_w_payload_data),
-    .io_ddrMasters_0_w_payload_strb     (io_ddrMasters_0_w_payload_strb),
-    .io_ddrMasters_0_w_payload_last     (io_ddrMasters_0_w_payload_last),
-    .io_ddrMasters_0_b_valid            (io_ddrMasters_0_b_valid),
-    .io_ddrMasters_0_b_ready            (io_ddrMasters_0_b_ready),
-    .io_ddrMasters_0_b_payload_id       (io_ddrMasters_0_b_payload_id),
-    .io_ddrMasters_0_b_payload_resp     (io_ddrMasters_0_b_payload_resp),
-    .io_ddrMasters_0_ar_valid           (io_ddrMasters_0_ar_valid),
-    .io_ddrMasters_0_ar_ready           (io_ddrMasters_0_ar_ready),
-    .io_ddrMasters_0_ar_payload_addr    (io_ddrMasters_0_ar_payload_addr),
-    .io_ddrMasters_0_ar_payload_id      (io_ddrMasters_0_ar_payload_id),
-    .io_ddrMasters_0_ar_payload_region  (io_ddrMasters_0_ar_payload_region),
-    .io_ddrMasters_0_ar_payload_len     (io_ddrMasters_0_ar_payload_len),
-    .io_ddrMasters_0_ar_payload_size    (io_ddrMasters_0_ar_payload_size),
-    .io_ddrMasters_0_ar_payload_burst   (io_ddrMasters_0_ar_payload_burst),
-    .io_ddrMasters_0_ar_payload_lock    (io_ddrMasters_0_ar_payload_lock),
-    .io_ddrMasters_0_ar_payload_cache   (io_ddrMasters_0_ar_payload_cache),
-    .io_ddrMasters_0_ar_payload_qos     (io_ddrMasters_0_ar_payload_qos),
-    .io_ddrMasters_0_ar_payload_prot    (io_ddrMasters_0_ar_payload_prot),
-    .io_ddrMasters_0_r_valid            (io_ddrMasters_0_r_valid),
-    .io_ddrMasters_0_r_ready            (io_ddrMasters_0_r_ready),
-    .io_ddrMasters_0_r_payload_data     (io_ddrMasters_0_r_payload_data),
-    .io_ddrMasters_0_r_payload_id       (io_ddrMasters_0_r_payload_id),
-    .io_ddrMasters_0_r_payload_resp     (io_ddrMasters_0_r_payload_resp),
-    .io_ddrMasters_0_r_payload_last     (io_ddrMasters_0_r_payload_last),
-    .io_ddrMasters_0_clk                (io_ddrMasters_0_clk),
-    .io_ddrMasters_0_reset              (io_ddrMasters_0_reset),
-    .io_ddrMasters_memCheck_pass        (io_ddrMasters_memCheck_pass),
-    .userInterruptA                     (userInterruptA),
-    .userInterruptB                     (userInterruptB),
-    .userInterruptC                     (userInterruptC),
-    .userInterruptD                     (userInterruptD),
-    .userInterruptE                     (userInterruptE),
-    .userInterruptF                     (userInterruptF),
-    .userInterruptH                     (userInterruptH),
-    .userInterruptG                     (userInterruptG),
-    .userInterruptI                     (userInterruptI),
-    .system_gpio_0_io_read              (system_gpio_0_io_read),
-    .system_gpio_0_io_write             (system_gpio_0_io_write),
-    .system_gpio_0_io_writeEnable       (system_gpio_0_io_writeEnable),
-    .system_uart_0_io_txd               (system_uart_0_io_txd),
-    .system_uart_0_io_rxd               (system_uart_0_io_rxd),
-    .system_spi_0_io_sclk_write         (system_spi_0_io_sclk_write),
-    .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable),
-    .system_spi_0_io_data_0_read        (system_spi_0_io_data_0_read),
-    .system_spi_0_io_data_0_write       (system_spi_0_io_data_0_write),
-    .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable),
-    .system_spi_0_io_data_1_read        (system_spi_0_io_data_1_read),
-    .system_spi_0_io_data_1_write       (system_spi_0_io_data_1_write),
-    .system_spi_0_io_data_2_writeEnable (system_spi_0_io_data_2_writeEnable),
-    .system_spi_0_io_data_2_read        (system_spi_0_io_data_2_read),
-    .system_spi_0_io_data_2_write       (system_spi_0_io_data_2_write),
-    .system_spi_0_io_data_3_writeEnable (system_spi_0_io_data_3_writeEnable),
-    .system_spi_0_io_data_3_read        (system_spi_0_io_data_3_read),
-    .system_spi_0_io_data_3_write       (system_spi_0_io_data_3_write),
-    .system_spi_0_io_ss                 (system_spi_0_io_ss),
-    .system_i2c_0_io_sda_writeEnable    (system_i2c_0_io_sda_writeEnable),
-    .system_i2c_0_io_sda_write          (system_i2c_0_io_sda_write),
-    .system_i2c_0_io_sda_read           (system_i2c_0_io_sda_read),
-    .system_i2c_0_io_scl_writeEnable    (system_i2c_0_io_scl_writeEnable),
-    .system_i2c_0_io_scl_write          (system_i2c_0_io_scl_write),
-    .system_i2c_0_io_scl_read           (system_i2c_0_io_scl_read),
-    .axiA_awaddr                        (axiA_awaddr),
-    .axiA_awlen                         (axiA_awlen),
-    .axiA_awsize                        (axiA_awsize),
-    .axiA_awburst                       (axiA_awburst),
-    .axiA_awlock                        (axiA_awlock),
-    .axiA_awcache                       (axiA_awcache),
-    .axiA_awprot                        (axiA_awprot),
-    .axiA_awqos                         (axiA_awqos),
-    .axiA_awregion                      (axiA_awregion),
-    .axiA_awvalid                       (axiA_awvalid),
-    .axiA_awready                       (axiA_awready),
-    .axiA_wdata                         (axiA_wdata),
-    .axiA_wstrb                         (axiA_wstrb),
-    .axiA_wvalid                        (axiA_wvalid),
-    .axiA_wlast                         (axiA_wlast),
-    .axiA_wready                        (axiA_wready),
-    .axiA_bresp                         (axiA_bresp),
-    .axiA_bvalid                        (axiA_bvalid),
-    .axiA_bready                        (axiA_bready),
-    .axiA_araddr                        (axiA_araddr),
-    .axiA_arlen                         (axiA_arlen),
-    .axiA_arsize                        (axiA_arsize),
-    .axiA_arburst                       (axiA_arburst),
-    .axiA_arlock                        (axiA_arlock),
-    .axiA_arcache                       (axiA_arcache),
-    .axiA_arprot                        (axiA_arprot),
-    .axiA_arqos                         (axiA_arqos),
-    .axiA_arregion                      (axiA_arregion),
-    .axiA_arvalid                       (axiA_arvalid),
-    .axiA_arready                       (axiA_arready),
-    .axiA_rdata                         (axiA_rdata),
-    .axiA_rresp                         (axiA_rresp),
-    .axiA_rlast                         (axiA_rlast),
-    .axiA_rvalid                        (axiA_rvalid),
-    .axiA_rready                        (axiA_rready),
-    .axiAInterrupt                      (axiAInterrupt),
-    .cfg_done                           (cfg_done),
-    .cfg_start                          (cfg_start),
-    .cfg_sel                            (cfg_sel),
-    .cfg_reset                          (cfg_reset),
-    .io_peripheralClk                   (io_peripheralClk),
-    .io_peripheralReset                 (io_peripheralReset),
-    .io_asyncReset                      (io_asyncReset),
-    .io_gpio_sw_n                       (io_gpio_sw_n),
-    .pll_peripheral_locked              (pll_peripheral_locked),
-    .pll_system_locked                  (pll_system_locked),
-    .pll_tse_locked                     (pll_tse_locked),
-    .sd_base_clk                        (sd_base_clk), 
-    .sd_clk_hi                          (sd_clk_hi),
-    .sd_clk_lo                          (sd_clk_lo),
-    .sd_cmd_i                           (sd_cmd_i),
-    .sd_cmd_o                           (sd_cmd_o),
-    .sd_cmd_oe                          (sd_cmd_oe),
-    .sd_dat_i                           (sd_dat_i),
-    .sd_dat_o                           (sd_dat_o),
-    .sd_dat_oe                          (sd_dat_oe),
-    .sd_cd_n                            (sd_cd_n), 
-    .sd_wp                              (sd_wp),
-    .io_tseClk                          (io_tseClk),
-    .rgmii_txd_HI                       (rgmii_txd_HI),
-    .rgmii_txd_LO                       (rgmii_txd_LO),
-    .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI),
-    .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO),
-    .rgmii_txc_HI                       (rgmii_txc_HI),
-    .rgmii_txc_LO                       (rgmii_txc_LO),
-    .rgmii_rxd_HI                       (rgmii_rxd_HI),
-    .rgmii_rxd_LO                       (rgmii_rxd_LO),
-    .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI),
-    .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO),
-    .mux_clk                            (mux_clk),
-    .mux_clk_sw                         (mux_clk_sw),
-    .phy_rst                            (phy_rst),
-    .phy_mdi                            (phy_mdi),
-    .phy_mdo                            (phy_mdo),
-    .phy_mdo_en                         (phy_mdo_en),
-    .phy_mdc                            (phy_mdc),
-    .rgmii_rxc                          (rgmii_rxc),
-    .rgmii_rxc_slow                     (rgmii_rxc_slow)
-);
-
-endmodule

src/sources.list

@@ -1,11 +1,11 @@
-regs/verilog6502_io_regs_pkg.sv
-regs/verilog6502_io_regs.sv
-verilog6502_addr_decoder.sv
-verilog6502_internal_memory.sv
-verilog6502_apb_adapter.sv
-verilog6502_external_memory.sv
-verilog6502_wrapper.sv
+embedded_wrapper/regs/verilog6502_io_regs_pkg.sv
+embedded_wrapper/regs/verilog6502_io_regs.sv
+embedded_wrapper/verilog6502_addr_decoder.sv
+embedded_wrapper/verilog6502_internal_memory.sv
+embedded_wrapper/verilog6502_apb_adapter.sv
+embedded_wrapper/verilog6502_external_memory.sv
+embedded_wrapper/verilog6502_embedded_wrapper.sv
 
 
-ALU.v
-cpu_65c02.v
+original_core/ALU.v
+original_core/cpu_65c02.v