Alex Mykyta
0ff68fade9
Add more doc notes regarding packed structs
2025-09-19 10:30:15 -07:00
Alex Mykyta
c1af43b0cc
Revise dependency constraints to use compatible versioning
2025-09-16 22:29:21 -07:00
Alex Mykyta
4c819b4bcb
fix doc phrasing
2025-08-08 17:05:58 -07:00
Alex Mykyta
17ceaa7c01
version
2025-07-16 10:53:20 -07:00
Alex Mykyta
c95c332bd0
Fix xsim errors for fixedpoint testcase
2025-07-16 10:17:11 -07:00
Alex Mykyta
588e1fee66
Add names to assertions. #151
2025-07-16 10:12:46 -07:00
Alex Mykyta
e96537fd5c
Fix incorrect NBA in Avalon always_comb template. #152
2025-07-16 08:10:39 -07:00
Alex Mykyta
a917164642
Tidy up whitespace in generated package. #148
2025-07-01 16:56:41 -07:00
Caio Alonso da Costa
105abdcba2
Update internal_protocol.rst ( #145 )
2025-06-06 14:16:02 -07:00
Alex Mykyta
8c0e772e0d
Switch docs theme
2025-05-19 10:10:35 -07:00
Alex Mykyta
9a0f6772d1
Update version
2025-05-15 22:14:39 -07:00
Dana Sorensen
d2b4911d5f
Add signed/fixedpoint properties ( #140 )
...
* declared intwidth, fracwidth, and is_signed UDPs
* fix boolean type name in UDP definition
* generate hwif fields with fixedpoint indices
* make "counter" and "encode" properties mutualy exclusive with signed/fixedpoint
* add signed/unsigned to hwif
* improved fixedpoint error messages, added validation tests
* added fixedpoint tests
* fixedpoint/signed not allowed for signal components
* added signed/fixedpoint UDP docs
* handle single-bit fixedpoint numbers
* fix too many positional arguments lint
* changed spelling of fixedpoint to fixed-point
* use "logic" in place of "unsigned logic"
* split signed and fixedpoint docs, added examples
* allow enums with is_signed=false
* split signed and fixedpoint implementations
* assorted nits picked
* updated is_signed validation unit test
2025-05-15 08:48:44 -07:00
Alex Mykyta
62f66fb7ff
Add xref to VHDL fork
2025-05-02 11:08:36 -07:00
Alex Mykyta
8216a9f2f3
Fix classifier
2025-04-11 22:30:22 -07:00
Alex Mykyta
833c515cd2
Re-enable xsim for testcases. Works better in Vivado 2024.2
2025-04-11 22:19:19 -07:00
Alex Mykyta
06bd567750
Increment version
2025-04-11 21:26:27 -07:00
Alex Mykyta
c3080d63ce
Add version_info tuple
2025-04-11 21:19:35 -07:00
Alex Mykyta
b95ba354c3
Add simulation-time width assertions to SV interfaces. #128
2025-04-11 21:14:15 -07:00
Alex Mykyta
48ae215eda
Add user parameters to regblock package. #112
2025-04-10 22:16:13 -07:00
Maciej Dudek
0a9a3ad51e
Allow for write enable and sticky property
...
This commit adds new type of fields: sticky with write enable.
This is used to gate status/interrupt register when one or more
interrupts aren't monitored.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com >
2025-04-10 21:45:57 -07:00
Maciej Dudek
a7cea87d40
Remove unreachable code
...
According to the SystemRDL specification interrupt can be either:
level, posedge, negedge, bothedge, or nonsticky.
This means that it's impossible to reach create filed that
satisfies [Pos|Neg|Both]edgeNonstickybit match functions.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com >
2025-04-10 21:45:56 -07:00
Alex Mykyta
4aed443c55
Make swmod respect cpuif byte strobes. #137
2025-04-10 21:26:08 -07:00
Alex Mykyta
bb2fead71a
Add FAQ to docs
2025-03-08 18:35:46 -08:00
Alex Mykyta
49e3311b85
cleanup text
2025-03-07 22:43:25 -08:00
Alex Mykyta
3ed2e1f891
Simplify stickybit implementation for single-bit fields to not create redundant expression. #127
2025-03-07 19:45:31 -08:00
Alex Mykyta
6430dd4914
Emit error if field that is asynchronously reset uses a dynamic reset value. #129
2025-03-07 19:20:44 -08:00
Alex Mykyta
d3cd51f500
Fix missing error message if multiple unconditional field assignments are inferred. #93
2025-03-06 22:12:26 -08:00
Alex Mykyta
54ac56e1c3
Add testcases to cover design validation errors
2025-03-06 22:10:05 -08:00
Alex Mykyta
f882e155d1
remove dead-code
2025-03-06 22:08:47 -08:00
Alex Mykyta
c53b11cf28
Add more specificity to stickybit conditional class
2025-03-06 21:24:49 -08:00
Alex Mykyta
40687abd6b
Type hinting cleanup
2025-03-03 21:37:07 -08:00
Alex Mykyta
0258cac186
drop py3.6. Misc housekeeping
2025-03-03 21:37:07 -08:00
Aylon Chaim Porat
28ed82129f
Add Addressmap block size to generated package ( #134 )
...
* add map size as a localparam in rdl map package
* rename from _SIZE -> _BYTES_SIZE
* fix names on new test & localparam
* wrap map size in SVInt
2025-03-03 21:16:25 -08:00
Alex Mykyta
aba2af17af
Increment version
2024-12-19 21:53:12 -08:00
Alex Mykyta
8d82eb29d9
Add width cast to address decode loop iterators. #92
2024-12-19 21:49:23 -08:00
Alex Mykyta
e788e7cafd
Remove excessive secondary counter saturation clamping logic. Counters will now be allowed to be set to values beyond their saturation point if loaded through non-increment/decrement mechanism. #114
2024-12-19 21:41:20 -08:00
Alex Mykyta
a15178c719
Use clog2 helper function to improve clarity. #116
2024-12-19 19:47:41 -08:00
Alex Mykyta
80a46a082b
Fix incorrect address width calculation for external blocks. #116
2024-12-19 19:40:57 -08:00
Alex Mykyta
5f9d7308c2
Add next_q storage element to reset clause to avoid synthesis issues with async resets. #113
2024-12-19 19:30:30 -08:00
Alex Mykyta
ebd82dde1b
Add peakrdl-cli optional dependency
2024-12-19 19:04:48 -08:00
Alex Mykyta
809195a72a
install mising test package
2024-12-18 22:21:35 -08:00
Alex Mykyta
1d7d47f49c
More type hint workarounds
2024-12-18 22:20:35 -08:00
Alex Mykyta
5c1bc35799
Type hint workarounds
2024-12-18 22:13:51 -08:00
Alex Mykyta
e0295ae526
Fixup test bitswap. mypy
2024-12-18 22:04:12 -08:00
Alex Mykyta
11d9f65dff
Fix incorrect bit-order in packed struct output of external registers. #111
2024-12-18 21:17:31 -08:00
Alex Mykyta
399f942201
Fix doc typos
2024-12-18 20:29:17 -08:00
Alex Mykyta
faa57c93b9
Add preprocessor ifndef around RTL assertions to allow exclusion. #104
2024-12-17 22:31:30 -08:00
Alex Mykyta
ceb1f9b0c1
Add contributing guidelines, issue templates, and PR template
2024-05-04 18:04:52 -07:00
Alex Mykyta
a076609dad
version
2024-03-31 22:21:54 -07:00
Alex Mykyta
4dfd9b10d6
Add support for CPUIFs to have parameters #80
2024-03-29 22:39:45 -07:00
