Commit Graph

245 Commits

Author SHA1 Message Date
Alex Mykyta
9fc95b8769 Refactor readback mux implementation. Improves performance (#155) and eliminates illegal streaming operator usage (#165) 2025-12-11 21:17:52 -08:00
Alex Mykyta
4201ce975e Fix OBI address truncation template for 1-byte datawidth case. #176 2025-11-18 22:45:30 -08:00
Alex Mykyta
61bffb7b91 Fix incorrect traversal into externals for read/write buffered regs. #167 2025-11-16 20:29:01 -08:00
Sebastien Baillou
efbddccc54 fix: handle error response for overlapped registers with read-only and write-only attributes (#178) 2025-11-15 19:33:21 -08:00
Sebastien Baillou
e1d7b3aa38 test: revert test_parity assign/deassign syntax with Xilinx simulator 2025-11-15 19:33:21 -08:00
Benjamin Davis
6597f889fa Improved the naming of tests which use the 'get_permutations' function. Adds the parameter values to the end of the test class. 2025-11-15 19:30:03 -08:00
Alex Mykyta
75a2163f6d doc updates 2025-11-15 14:47:16 -08:00
Alex Mykyta
7f572e05a4 Remove dangerous usage of non-public parts of the systemrdl-compiler API 2025-11-15 12:23:53 -08:00
Benjamin Davis
610351d169 Fixed VSIM-7061 error in test_parity when using latest Questa Simulator. (#182)
Closes #181
2025-11-13 21:26:18 -08:00
Benjamin Davis
3d5f9d8efb Added the ability to specify a regex filter for the part-name on the synthesis tests. Implemented as --synth-part. Closes #179 (#180) 2025-11-13 20:09:03 -08:00
Alex Mykyta
543bf2be9a Remove dangerous usage of non-public parts of the systemrdl-compiler API 2025-11-04 23:05:50 -08:00
Alex Mykyta
17465e5f97 version 2025-11-04 21:37:33 -08:00
Alex Mykyta
fcf4bffeb7 add missing docs 2025-11-04 21:28:51 -08:00
Alex Mykyta
ef2a18c8c0 Fix missing address truncation in OBI. #173 2025-11-04 21:21:53 -08:00
Alex Mykyta
529c4df98c Move port list generation out of Jinja template. #125, #153 2025-10-25 20:19:15 -07:00
Alex Mykyta
1926aff7b1 Add missing comment for external components 2025-10-25 19:23:28 -07:00
sbaillou
d69af23be5 Error response for unmapped address or forbidden read/write access (#168)
* feat: add ability to enable error output on the cpuif, when decoding errors occur (generate_cpuif_err in API).

* fix: move signal to new place (after automatic vers)

* feat: add info about new api (generate_cpuif_err)

* fix: repair readback with latency

* Adding generate_cpuif_err argument to peakrdl-regblock to generate cpuif error response, when the address is decoded incorrectly

* add sw rd or/and wr attribure error response related and add error respone for external mem

* add sw rd or/and wr error response test

* add sw rd or/and wr error response for external register test and fix generation of rtl logic for external register

* add sw rd or/and wr error response for external mem test

* add sw rd or/and wr error response for apb3 imterfaces driver

* add error response test for APB4, AXI4Lite and Avalon interfaces

* rename --generate_cpuif_err to --generate-cpuif-err

* style: minor typo fixes and test clean-up

* refactor: move expected error check inside write/read functions

* feat: add error response check to OBI testbench interface

* feat: split generate-cpuif-err option into err-if-bad-addr and err-if-bad-rw options

* feat: add err_if_bad_addr/rw to cfg_schema

* feat: extend cpuif_err_rsp test to cover all combinations of bad_addr/bad_rw

* style: lint fixes

* fix: removed redundant if node.external condition to help coverage

* Fix dangling hwif_in signals in testcase

---------

Co-authored-by: Denis Trifonov <d.trifonov@yadro.com>
Co-authored-by: Dominik Tanous <tanous@kandou.com>
Co-authored-by: Sebastien Baillou <baillou@kandou.com>
Co-authored-by: Alex Mykyta <amykyta3@users.noreply.github.com>
2025-10-25 18:22:15 -07:00
Alex Mykyta
bb765e6ae3 Add 's_' prefix to OBI port for consistency with all other cpuifs 2025-10-25 17:24:57 -07:00
Alex Mykyta
dafd693a1d OBI: Add testcase support. #157 2025-10-24 19:36:36 -07:00
Alex Mykyta
f782c656ca OBI: Fix missing intf definition. Adjust coding style. #157 2025-10-24 18:46:16 -07:00
Daniel Keller
aa9a21046d feat: Add support for OBI protocol (#158)
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
2025-10-24 18:46:16 -07:00
Dana Sorensen
18cf2aabc7 don't emit write/read-buffer logic for external components 2025-10-24 18:41:18 -07:00
Dana Sorensen
087b1f8611 added failing tests for external write/read-buffered components 2025-10-24 18:41:18 -07:00
Alex Mykyta
b097062e85 bump py versions 2025-10-13 22:42:40 -07:00
Sebastien Baillou
a440cc1976 Add Xcelium simulator option 2025-10-10 09:58:36 -07:00
Alex Mykyta
08c24d4784 Switch to LGPLv3 license 2025-10-07 09:33:17 -07:00
Alex Mykyta
0ff68fade9 Add more doc notes regarding packed structs 2025-09-19 10:30:15 -07:00
Alex Mykyta
c1af43b0cc Revise dependency constraints to use compatible versioning 2025-09-16 22:29:21 -07:00
Alex Mykyta
4c819b4bcb fix doc phrasing 2025-08-08 17:05:58 -07:00
Alex Mykyta
17ceaa7c01 version 2025-07-16 10:53:20 -07:00
Alex Mykyta
c95c332bd0 Fix xsim errors for fixedpoint testcase 2025-07-16 10:17:11 -07:00
Alex Mykyta
588e1fee66 Add names to assertions. #151 2025-07-16 10:12:46 -07:00
Alex Mykyta
e96537fd5c Fix incorrect NBA in Avalon always_comb template. #152 2025-07-16 08:10:39 -07:00
Alex Mykyta
a917164642 Tidy up whitespace in generated package. #148 2025-07-01 16:56:41 -07:00
Caio Alonso da Costa
105abdcba2 Update internal_protocol.rst (#145) 2025-06-06 14:16:02 -07:00
Alex Mykyta
8c0e772e0d Switch docs theme 2025-05-19 10:10:35 -07:00
Alex Mykyta
9a0f6772d1 Update version 2025-05-15 22:14:39 -07:00
Dana Sorensen
d2b4911d5f Add signed/fixedpoint properties (#140)
* declared intwidth, fracwidth, and is_signed UDPs

* fix boolean type name in UDP definition

* generate hwif fields with fixedpoint indices

* make "counter" and "encode" properties mutualy exclusive with signed/fixedpoint

* add signed/unsigned to hwif

* improved fixedpoint error messages, added validation tests

* added fixedpoint tests

* fixedpoint/signed not allowed for signal components

* added signed/fixedpoint UDP docs

* handle single-bit fixedpoint numbers

* fix too many positional arguments lint

* changed spelling of fixedpoint to fixed-point

* use "logic" in place of "unsigned logic"

* split signed and fixedpoint docs, added examples

* allow enums with is_signed=false

* split signed and fixedpoint implementations

* assorted nits picked

* updated is_signed validation unit test
2025-05-15 08:48:44 -07:00
Alex Mykyta
62f66fb7ff Add xref to VHDL fork 2025-05-02 11:08:36 -07:00
Alex Mykyta
8216a9f2f3 Fix classifier 2025-04-11 22:30:22 -07:00
Alex Mykyta
833c515cd2 Re-enable xsim for testcases. Works better in Vivado 2024.2 2025-04-11 22:19:19 -07:00
Alex Mykyta
06bd567750 Increment version 2025-04-11 21:26:27 -07:00
Alex Mykyta
c3080d63ce Add version_info tuple 2025-04-11 21:19:35 -07:00
Alex Mykyta
b95ba354c3 Add simulation-time width assertions to SV interfaces. #128 2025-04-11 21:14:15 -07:00
Alex Mykyta
48ae215eda Add user parameters to regblock package. #112 2025-04-10 22:16:13 -07:00
Maciej Dudek
0a9a3ad51e Allow for write enable and sticky property
This commit adds new type of fields: sticky with write enable.
This is used to gate status/interrupt register when one or more
interrupts aren't monitored.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2025-04-10 21:45:57 -07:00
Maciej Dudek
a7cea87d40 Remove unreachable code
According to the SystemRDL specification interrupt can be either:
level, posedge, negedge, bothedge, or nonsticky.
This means that it's impossible to reach create filed that
satisfies [Pos|Neg|Both]edgeNonstickybit match functions.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2025-04-10 21:45:56 -07:00
Alex Mykyta
4aed443c55 Make swmod respect cpuif byte strobes. #137 2025-04-10 21:26:08 -07:00
Alex Mykyta
bb2fead71a Add FAQ to docs 2025-03-08 18:35:46 -08:00
Alex Mykyta
49e3311b85 cleanup text 2025-03-07 22:43:25 -08:00