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Add divider

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Adds a 16x16 divider to go with the multiplier.

The divider is a single stage with no pipelining, which works at the
slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5.

This is acceptable for now but means that the cpu can't be run at 14,
which is the maximum frequency.
This commit is contained in:
Byron Lathi
2023-01-05 18:35:42 -05:00
parent 42ad901ba4
commit 5f6657a227
14 changed files with 1585 additions and 438 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hw/efinix_fpga/addr_decode.sv
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@@ -6,12 +6,14 @@ module addr_decode
output o_leds_cs,
output o_timer_cs,
output o_multiplier_cs,
output o_divider_cs,
output o_sdram_cs
);
assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
assign o_divider_cs = i_addr >= 16'hefe7 && i_addr <= 16'hefef;
assign o_leds_cs = i_addr == 16'hefff;
assign o_sdram_cs = i_addr < 16'h8000;

1261
hw/efinix_fpga/debug_profile.wizard.json
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File diff suppressed because it is too large Load Diff

82
hw/efinix_fpga/divider_wrapper.sv Normal file
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@@ -0,0 +1,82 @@
module divider_wrapper(
input clk,
input reset,
input [7:0] i_data,
output logic [7:0] o_data,
input cs,
input rwb,
input [2:0] addr
);
logic [15:0] numer, denom;
logic [15:0] quotient, remain;
logic clken, rfd;
assign clken = '1;
divider u_divider(
.numer ( numer ),
.denom ( denom ),
.clken ( clken ),
.clk ( clk ),
.reset ( reset ),
.quotient ( quotient ),
.remain ( remain ),
.rfd ( rfd )
);
always_ff @(negedge clk) begin
if (reset) begin
numer <= '0;
denom <= '0;
end
if (cs & ~rwb) begin
case (addr)
3'h0: begin
numer[7:0] <= i_data;
end
3'h1: begin
numer[15:8] <= i_data;
end
3'h2: begin
denom[7:0] <= i_data;
end
3'h3: begin
denom[15:8] <= i_data;
end
endcase
end
end
always_comb begin
case (addr)
3'h4: begin
o_data = quotient[7:0];
end
3'h5: begin
o_data = quotient[15:8];
end
3'h6: begin
o_data = remain[7:0];
end
3'h7: begin
o_data = remain[15:8];
end
endcase
end
endmodule

4
hw/efinix_fpga/ip/bram/bram_ini.vh
View File

@@ -4,8 +4,8 @@ input integer index;//Mode type
input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved
case (index)
0: bram_ini_table=
(val_== 0)?256'h008d000c8000a9000ef000f10008d00000000a9000ef000f00008d0007b000a9:
(val_== 1)?256'h0ef000ff0008d000ef000f5000ad000ef000f30008d00001000a9000ef000f20:
(val_== 0)?256'h008d0000d000a9000ef000e90008d00001000a9000ef000e80008d000c8000a9:
(val_== 1)?256'h0ef000ff0008d000ef000ec000ad000ef000eb0008d00000000a9000ef000ea0:
(val_== 2)?256'h00000000000000000000000000000000000000000000000000e300080000cb00:
(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:

26
hw/efinix_fpga/ip/bram/init_hex.mem
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@@ -1,25 +1,25 @@
a9
7b
8d
f0
ef
a9
00
8d
f1
ef
a9
c8
8d
f2
e8
ef
a9
01
8d
f3
e9
ef
a9
0d
8d
ea
ef
a9
00
8d
eb
ef
ad
f5
ec
ef
8d
ff

390
hw/efinix_fpga/ip/divider/divider.v Normal file
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@@ -0,0 +1,390 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2022.2.322
// IP Version: 2.2
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
`define IP_UUID _1d82aa757d4b4554a855552eadc85243
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module divider (
input [15:0] numer,
input [15:0] denom,
input clken,
input clk,
input reset,
output [15:0] quotient,
output [15:0] remain,
output rfd
);
`IP_MODULE_NAME(divider) #(
.NREPRESENTATION ("UNSIGNED"),
.WIDTHN (16),
.WIDTHD (16),
.DREPRESENTATION ("UNSIGNED"),
.PIPELINE (0),
.LATENCY (0)
) u_divider(
.numer ( numer ),
.denom ( denom ),
.clken ( clken ),
.clk ( clk ),
.reset ( reset ),
.quotient ( quotient ),
.remain ( remain ),
.rfd ( rfd )
);
endmodule
`timescale 1ns / 1ps
module `IP_MODULE_NAME(divider) (
clk,
reset,
numer,
denom,
quotient,
remain,
rfd,
clken
);
parameter WIDTHN = 8;
parameter WIDTHD = 8;
parameter LATENCY = 8;
parameter PIPELINE = 1;
parameter NREPRESENTATION = "UNSIGNED";
parameter DREPRESENTATION = "UNSIGNED";
parameter ENABLE_OUTREG = 0;
input clk;
input reset;
input clken;
input [(WIDTHN-1):0] numer;
input [(WIDTHD-1):0] denom;
//output
output reg rfd;
output reg [(WIDTHN-1):0] quotient;
output reg [(WIDTHD-1):0] remain;
wire [WIDTHN-1:0] numer_temp;
wire [WIDTHD-1:0] denom_temp;
wire sign_numer;
wire sign_denom;
wire [(WIDTHN-1):0] quotient_copy;
wire [(WIDTHD-1):0] remain_copy;
reg sign_quotient[LATENCY:0];
genvar i, j;
// Main operation
generate begin
if(NREPRESENTATION == "SIGNED") begin
assign numer_temp = (numer[(WIDTHN-1)] == 1'b1) ? (~numer + 1) : numer;
assign sign_numer = (numer[(WIDTHN-1)] == 1'b1) ? 1'b1 : 1'b0;
end
else begin
assign numer_temp = numer;
assign sign_numer = 1'b0;
end
if(DREPRESENTATION == "SIGNED") begin
assign denom_temp = (denom[(WIDTHD-1)] == 1'b1) ? (~denom + 1) : denom;
assign sign_denom = (denom[(WIDTHD-1)] == 1'b1) ? 1'b1 : 1'b0;
end
else begin
assign denom_temp = denom;
assign sign_denom = 1'b0;
end
always @* begin
sign_quotient[0] = sign_numer ^ sign_denom;
end
for (i=0; i<LATENCY; i=i+1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
sign_quotient[i+1] <= 1'b0;
end
else if(clken) begin
sign_quotient[i+1] <= sign_quotient[i];
end
end
end
if (PIPELINE) begin : pipeline
wire [(WIDTHN+1):0] sub[WIDTHN-1:0];
reg [WIDTHN-1:0] quotient_temp[WIDTHN:0];
reg [WIDTHN-1:0] remain_temp[WIDTHN:0];
reg [WIDTHN-1:0] denom_copy[WIDTHN:0];
always @* begin
rfd = 1'b0; //for PIPELINE enable, rfd is not used
denom_copy[0] = denom_temp;
remain_temp[0] = {WIDTHN{1'b0}};
quotient_temp[0] = numer_temp;
end
for (i=0; i<WIDTHN; i=i+1) begin
assign sub[i] = {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]} - denom_copy[i];
if (i < LATENCY) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
remain_temp[i+1] <= {WIDTHN{1'b0}};
quotient_temp[i+1] <= {WIDTHN{1'b0}};
denom_copy[i+1] <= {WIDTHN{1'b0}};
end
else if(clken) begin
denom_copy[i+1] <= denom_copy[i];
if (sub[i][(WIDTHN)] == 0) begin
remain_temp[i+1] <= sub[i][(WIDTHN-1):0];
quotient_temp[i+1] <= {quotient_temp[i][(WIDTHN-2):0], 1'b1};
end
else begin
remain_temp[i+1] <= {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]};
quotient_temp[i+1] <= {quotient_temp[i][(WIDTHN-2):0], 1'b0};
end
end
end
end
else begin
always @* begin
denom_copy[i+1] = denom_copy[i];
end
always @* begin
if (sub[i][(WIDTHN)] == 0) begin
remain_temp[i+1] = sub[i][(WIDTHN-1):0];
end
else begin
remain_temp[i+1] = {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]};
end
end
always @* begin
if (sub[i][(WIDTHN)] == 0) begin
quotient_temp[i+1] = {quotient_temp[i][(WIDTHN-2):0], 1'b1};
end
else begin
quotient_temp[i+1] = {quotient_temp[i][(WIDTHN-2):0], 1'b0};
end
end
end
end
if (NREPRESENTATION == "SIGNED" || DREPRESENTATION == "SIGNED") begin
assign quotient_copy = sign_quotient[LATENCY] ? (~quotient_temp[WIDTHN] + 1) : quotient_temp[WIDTHN];
end
else begin
assign quotient_copy = quotient_temp[WIDTHN];
end
assign remain_copy = remain_temp[WIDTHN];
end
else begin : non_pipeline
localparam COMBI_STAGE = WIDTHN - LATENCY;
wire [(WIDTHN-1):0] denom_sub;
reg [WIDTHN-1:0] denom_reg;
reg [(WIDTHN-1):0] quotient_reg;
reg [(WIDTHN-1):0] remain_reg;
wire [(WIDTHN+1):0] sub;
reg [(WIDTHN-1):0] quotient_combi[COMBI_STAGE:0];
reg [WIDTHN-1:0] remain_combi[COMBI_STAGE:0];
wire [(WIDTHN+1):0] sub_combi[COMBI_STAGE:0];
reg clken_IP;
assign denom_sub = {{(WIDTHN-WIDTHD){1'b0}},denom_temp};
always @(posedge clk,posedge reset) begin
if(reset) begin
clken_IP <= 1'b0;
end
else begin
clken_IP <= clken;
end
end
if(LATENCY > 0) begin
reg [LATENCY-1:0] ready;
assign sub = (ready[0] || ~clken_IP) ? ({{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]} - denom_sub) : ({remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]} - denom_reg);
always @(posedge clk,posedge reset) begin
if(reset) begin
ready <= {LATENCY{1'b0}};
end
else if(clken) begin
if(ready[0] || ~clken_IP) begin
ready <= {1'b1, {LATENCY-1{1'b0}}};
end
else begin
ready <= {1'b0, ready[LATENCY-1:1]};
end
end
else begin
ready <= {LATENCY{1'b0}};
end
end
always @(posedge clk,posedge reset) begin
if(reset) begin
remain_reg <= {WIDTHN{1'b0}};
quotient_reg <= {WIDTHN{1'b0}};
denom_reg <= {WIDTHN{1'b0}};
end
else if(clken) begin
if(ready[0] || ~clken_IP) begin
denom_reg <= denom_temp;
if (sub[(WIDTHN)] == 0) begin
remain_reg <= sub[(WIDTHN-1):0];
quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b1};
end
else begin
remain_reg <= {{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]};
quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b0};
end
end
else begin
if (sub[(WIDTHN)] == 0) begin
remain_reg <= sub[(WIDTHN-1):0];
quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b1};
end
else begin
remain_reg <= {remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]};
quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b0};
end
end
end
end
if (ENABLE_OUTREG) begin
always @(posedge clk,posedge reset) begin
if (reset) begin
rfd <= 1'b0;
end
else begin
rfd <= ready[0];
end
end
end
else begin
always @* begin
rfd = ready[0];
end
end
always @* begin
quotient_combi[0] = quotient_reg;
remain_combi[0] = remain_reg;
end
for (i=0; i<COMBI_STAGE; i=i+1) begin
assign sub_combi[i] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]} - denom_reg;
end
end
else begin
always @* begin
rfd = 1'b1;
end
always @* begin
quotient_combi[0] = numer_temp;
remain_combi[0] = {WIDTHN{1'b0}};
end
for (i=0; i<COMBI_STAGE; i=i+1) begin
assign sub_combi[i] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]} - denom_sub;
end
end
for (i=0; i<COMBI_STAGE; i=i+1) begin
always @* begin
if(sub_combi[i][(WIDTHN)] == 0) begin
remain_combi [i+1] = sub_combi[i][(WIDTHN-1):0];
quotient_combi [i+1] = {quotient_combi[i][(WIDTHN-2):0], 1'b1};
end
else begin
remain_combi[i+1] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]};
quotient_combi[i+1] = {quotient_combi[i][(WIDTHN-2):0], 1'b0};
end
end
end
if(NREPRESENTATION == "SIGNED" || DREPRESENTATION == "SIGNED") begin
assign quotient_copy = sign_quotient[LATENCY] ? (~quotient_combi[COMBI_STAGE] + 1): quotient_combi[COMBI_STAGE];//
end
else begin
assign quotient_copy = quotient_combi[COMBI_STAGE];
end
assign remain_copy = remain_combi[COMBI_STAGE];
end
if (ENABLE_OUTREG) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
quotient <= {WIDTHN{1'b0}};
remain <= {WIDTHD{1'b0}};
end
else begin
quotient <= quotient_copy;
remain <= remain_copy;
end
end
end
else begin
always @* begin
quotient = quotient_copy;
remain = remain_copy;
end
end
end
endgenerate
endmodule
`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME

51
hw/efinix_fpga/ip/divider/divider_define.vh Normal file
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@@ -0,0 +1,51 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2022.2.322
// IP Version: 2.2
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam NREPRESENTATION = "UNSIGNED";
localparam WIDTHN = 16;
localparam WIDTHD = 16;
localparam DREPRESENTATION = "UNSIGNED";
localparam PIPELINE = 0;
localparam LATENCY = 0;

49
hw/efinix_fpga/ip/divider/divider_tmpl.v Normal file
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@@ -0,0 +1,49 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
divider u_divider(
.numer ( numer ),
.denom ( denom ),
.clken ( clken ),
.clk ( clk ),
.reset ( reset ),
.quotient ( quotient ),
.remain ( remain ),
.rfd ( rfd )
);

64
hw/efinix_fpga/ip/divider/divider_tmpl.vhd Normal file
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@@ -0,0 +1,64 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT divider is
PORT (
numer : in std_logic_vector(15 downto 0);
denom : in std_logic_vector(15 downto 0);
clken : in std_logic;
clk : in std_logic;
reset : in std_logic;
quotient : out std_logic_vector(15 downto 0);
remain : out std_logic_vector(15 downto 0);
rfd : out std_logic);
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_divider : divider
PORT MAP (
numer => numer,
denom => denom,
clken => clken,
clk => clk,
reset => reset,
quotient => quotient,
remain => remain,
rfd => rfd);
------------------------ End INSTANTIATION Template ---------

33
hw/efinix_fpga/ip/divider/settings.json Normal file
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@@ -0,0 +1,33 @@
{
"args": [
"-o",
"divider",
"--base_path",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "arithmetic",
"name": "efx_divider",
"version": "2.2"
}
],
"conf": {
"NREPRESENTATION": "0",
"WIDTHN": "16",
"WIDTHD": "16",
"DREPRESENTATION": "0",
"PIPELINE": "0",
"LATENCY": "0"
},
"output": {
"external_source_source": [
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_define.vh",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_tmpl.vhd",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_tmpl.v"
]
},
"sw_version": "2022.2.322",
"generated_date": "2023-01-05T22:36:48.178317"
}

15
hw/efinix_fpga/super6502.sv
View File

@@ -67,6 +67,7 @@ logic w_leds_cs;
logic w_sdram_cs;
logic w_timer_cs;
logic w_multiplier_cs;
logic w_divider_cs;
addr_decode u_addr_decode(
.i_addr(cpu_addr),
@@ -74,6 +75,7 @@ addr_decode u_addr_decode(
.o_leds_cs(w_leds_cs),
.o_timer_cs(w_timer_cs),
.o_multiplier_cs(w_multiplier_cs),
.o_divider_cs(w_divider_cs),
.o_sdram_cs(w_sdram_cs)
);
@@ -81,6 +83,7 @@ logic [7:0] w_rom_data_out;
logic [7:0] w_leds_data_out;
logic [7:0] w_timer_data_out;
logic [7:0] w_multiplier_data_out;
logic [7:0] w_divider_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
@@ -92,6 +95,8 @@ always_comb begin
cpu_data_out = w_timer_data_out;
else if (w_multiplier_cs)
cpu_data_out = w_multiplier_data_out;
else if (w_divider_cs)
cpu_data_out = w_divider_data_out;
else if (w_sdram_cs)
cpu_data_out = w_sdram_data_out;
else
@@ -142,6 +147,16 @@ multiplier u_multiplier(
.addr(cpu_addr[2:0])
);
divider_wrapper u_divider(
.clk(clk_2),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_divider_data_out),
.cs(w_divider_cs),
.rwb(cpu_rwb),
.addr(cpu_addr[2:0])
);
sdram_adapter u_sdram_adapter(
.i_cpuclk(clk_2),
.i_arst(~button_reset),

11
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Wed January 4 2023 15:54:48" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Thu January 5 2023 18:30:12" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -19,6 +19,7 @@
<efx:design_file name="timer.sv" version="default" library="default"/>
<efx:design_file name="interrupt_controller.sv" version="default" library="default"/>
<efx:design_file name="multiplier.sv" version="default" library="default"/>
<efx:design_file name="divider_wrapper.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
@@ -31,6 +32,9 @@
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
<efx:ip_src_file name="sdram_controller.v"/>
</efx:ip>
<efx:ip instance_name="divider" path="ip/divider/settings.json">
<efx:ip_src_file name="divider.v"/>
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
@@ -55,8 +59,9 @@
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="include" value="ip/divider" value_type="e_string"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
@@ -89,7 +94,7 @@
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
</efx:debugger>
</efx:project>

2
hw/efinix_fpga/test_programs/Makefile
View File

@@ -1,4 +1,4 @@
TARGETS=stacktest runram timer timer_irq multiplier
TARGETS=stacktest runram timer timer_irq multiplier divider
SRC=$(wildcard *.s)
DIR=../ip/bram

33
hw/efinix_fpga/test_programs/divider.s Normal file
View File

@@ -0,0 +1,33 @@
.code
LEDS = $efff
DIVNL = $efe8
DIVNH = $efe9
DIVDL = $efea
DIVDH = $efeb
DIVQL = $efec
DIVQH = $efed
DIVRL = $efee
DIVRH = $efef
main:
lda #$c8
sta DIVNL
lda #$01
sta DIVNH
lda #$0d
sta DIVDL
lda #$00
sta DIVDH
lda DIVQL
sta LEDS
wai
bra main
.segment "VECTORS"
.addr main
.addr main
.addr main