Byron Lathi
2f6c1bff83
Merge branch '82-add-axi-sd-card-controller' into 'AXI-Rewrite'
...
Resolve "Add AXI SD Card controller"
Closes #82
See merge request bslathi19/super6502!70
2024-03-18 06:19:37 +00:00
Byron Lathi
25f51deaa7
Synthesize sd card dma
2024-03-17 22:26:42 -07:00
Byron Lathi
9b50dab855
Update submodules, update sources
2024-03-15 21:02:53 -07:00
Byron Lathi
eb5c3b0b02
Update verilog sd to get up to cmd7
2024-03-14 19:34:04 -07:00
Byron Lathi
0f9e470d13
Update rtl common since I commited to the wrong branch (again)
2024-03-14 19:20:08 -07:00
Byron Lathi
4028c2a36e
Update rtl common since I commited to the wrong branch
2024-03-14 17:14:38 -07:00
Byron Lathi
335f877d66
Run simulation with verilog sd emulator
...
This also slowed the cpu clock down, we should speed it up again
2024-03-14 08:17:05 -07:00
Byron Lathi
24a7001aee
Add sd mode sd card emulator
2024-03-13 00:01:39 -07:00
Byron Lathi
262c4cfd83
Add sd emulator (need to add sd mode)
2024-03-12 22:14:02 -07:00
Byron Lathi
14cf303c9f
Update sd controller for sim
2024-03-12 21:51:55 -07:00
Byron Lathi
02097ff3b8
Update sd controller with data host
2024-03-12 20:23:41 -07:00
Byron Lathi
455814ec14
Update sd controller and test code
2024-03-12 18:20:51 -07:00
Byron Lathi
f7580f719f
Add program target to makefiles
2024-03-10 22:25:29 -07:00
Byron Lathi
61f6e53327
Updates based on fpga test
...
1. in SD mode, CMD0 does not have a response, so we specifically ignore
it.
2. The penable signal was messed up, although it looks like this doesn't
matter anyway
3. The SD clock should be out of phase from the data signal by 180
degrees, so that we get max hold time
2024-03-10 22:09:55 -07:00
Byron Lathi
3c0bf9740c
Delete init hex on clean
2024-03-10 21:56:48 -07:00
Byron Lathi
142759ff59
Require python3.11
2024-03-10 16:42:21 -07:00
Byron Lathi
d3914b3a51
Add sd io pins
2024-03-10 16:09:12 -07:00
Byron Lathi
8f6d074255
Re-order init script to fix python import issue in synthesis
2024-03-10 12:55:38 -07:00
Byron Lathi
cb426670cd
Do synthesis with sd controller
2024-03-10 12:29:08 -07:00
Byron Lathi
da41e60ee7
integrate sd controller and super simple tb
2024-03-10 11:31:07 -07:00
Byron Lathi
81382925f8
Update rtl common and sd controller submodules
2024-03-10 10:24:50 -07:00
Byron Lathi
96e014567d
Add sd controller submodule
2024-03-04 00:06:29 -08:00
Byron Lathi
cf693a28d6
Merge branch '79-add-sdram' into 'AXI-Rewrite'
...
Resolve "Add SDRAM"
Closes #79
See merge request bslathi19/super6502!69
2024-03-04 07:38:13 +00:00
Byron Lathi
38c64e5551
Add sdram io to fpga
2024-03-03 23:35:25 -08:00
Byron Lathi
358dfdbe75
Add sdram io to fpga
2024-03-03 23:31:02 -08:00
Byron Lathi
aee04b777a
Fix sdram sim
...
Just need to add the RTL_SIM define
2024-03-03 21:33:28 -08:00
Byron Lathi
10a72d8e1f
Add sdram, don't think it works though
2024-03-03 20:43:37 -08:00
Byron Lathi
78dfb01bd7
Merge branch '81-add-simulation' into 'AXI-Rewrite'
...
Resolve "Add simulation"
Closes #81
See merge request bslathi19/super6502!68
2024-03-04 01:24:49 +00:00
Byron Lathi
12f54e7358
Merge branch '78-add-basic-software' into 81-add-simulation
2024-03-03 17:17:13 -08:00
Byron Lathi
01b1ecbcac
Add basic sim
2024-03-03 17:09:17 -08:00
Byron Lathi
3a9b967a5d
Merge branch '78-add-basic-software' into 'AXI-Rewrite'
...
Resolve "Add Basic Software"
Closes #78
See merge request bslathi19/super6502!67
2024-03-03 23:17:39 +00:00
Byron Lathi
ab9da189d1
Build software correctly, ignore debugger files
2024-03-03 14:50:40 -08:00
Byron Lathi
a343b23ddd
Make a venv in build
2024-03-03 13:13:41 -08:00
Byron Lathi
d60d7a25b2
Build everything in ci
2024-03-03 13:06:56 -08:00
Byron Lathi
42fbc17a2a
Add test code and top level Makefile
2024-03-03 12:52:44 -08:00
Byron Lathi
0ba5888aa1
Merge branch '77-add-axi-cpu-and-ram' into 'AXI-Rewrite'
...
Resolve "Add axi cpu and ram"
Closes #77
See merge request bslathi19/super6502!66
2024-03-03 19:38:10 +00:00
Byron Lathi
cd1dfa39cb
Fix PLL settings, add cpu output clock
2024-03-03 09:45:04 -08:00
Byron Lathi
6213d2a227
Use relative submodule paths for ci
2024-03-02 23:47:13 -08:00
Byron Lathi
31b3fdcfc9
Add basic ci and separate hw from all target
2024-03-02 22:55:39 -08:00
Byron Lathi
0752220b0e
Add basic project with cpu, ram and rom
2024-03-02 22:46:48 -08:00
Byron Lathi
0a0394ae33
Delete everything
2024-03-02 20:11:33 -08:00
Byron Lathi
273484b994
Merge branch '15-parse-the-read-only-file-system' into 'master'
...
Resolve "Parse the read-only file system"
Closes #15
See merge request bslathi19/super6502!64
2023-12-09 07:28:55 +00:00
Byron Lathi
0aca4af272
Add fixes for multiple sectors per cluster
2023-12-08 23:11:52 -08:00
Byron Lathi
5259fa8e65
Clear the carry flag, not the interrupt flag...
2023-12-08 08:12:50 -08:00
Byron Lathi
15e9b44318
Try clearing carry flag, that always helps. Also don't need verilog image anymore
2023-12-07 23:29:18 -08:00
Byron Lathi
6f16ac4daf
Add close, add filesystem code to main kernel for hardware testing
2023-12-07 08:10:45 -08:00
Byron Lathi
0327ab6a2b
Handle non-aligned reads
2023-12-06 21:02:41 -08:00
Byron Lathi
066bb0ee8c
Get read working a little bit more. Need to handle edge cases!
2023-12-05 23:29:00 -08:00
Byron Lathi
4c3c3fd731
Get something working with read
...
It is not reading offset correctly
2023-12-05 22:47:24 -08:00
Byron Lathi
48b39eb92d
Hack together open()
2023-12-05 19:10:27 -08:00
