Alex Forencich
|
08879e80b8
|
eth: Mask off end of packet when lane swapped
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:12:20 -07:00 |
|
Alex Forencich
|
59a3d5f511
|
eth: Normalize signal and register names in MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:11:27 -07:00 |
|
Alex Forencich
|
2810b72147
|
eth: Decoding is don't care with termination in lane 0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 21:59:20 -07:00 |
|
Alex Forencich
|
caeacadb78
|
eth: Clean up masking, lane 0 never needs to be masked
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 20:06:58 -07:00 |
|
Alex Forencich
|
93ef0f970b
|
eth: Re-nest if statements for termination character handling in 10G RX logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 19:01:47 -07:00 |
|
Alex Forencich
|
e395398666
|
eth: Rework input encoding in BASE-R RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 18:43:20 -07:00 |
|
Alex Forencich
|
7e08164e8d
|
eth: Add term_first_cycle_reg to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 17:01:53 -07:00 |
|
Alex Forencich
|
879b65cc70
|
eth: Normalize CRC register naming in 10G RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 15:54:49 -07:00 |
|
Alex Forencich
|
d0d6747f88
|
eth: Merge lane swapping logic into BASE-R encode logic in 64-bit BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 11:47:21 -07:00 |
|
Alex Forencich
|
0e2acbf482
|
eth: Fix 2D array declarations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 11:02:30 -07:00 |
|
Alex Forencich
|
5dff55ec06
|
lfsr: Remove extraneous data mask init
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 22:08:57 -07:00 |
|
Alex Forencich
|
04df834708
|
eth: Optimize frame length enforcement logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 15:49:51 -07:00 |
|
Alex Forencich
|
8257fdf09e
|
eth: Remove unused encodings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 13:47:52 -07:00 |
|
Alex Forencich
|
144537126a
|
axis: Remove extraneous generate block in async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 23:36:25 -07:00 |
|
Alex Forencich
|
f4e36bd081
|
eth: Optimize padding logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 23:08:11 -07:00 |
|
Alex Forencich
|
7e629d934f
|
Fix TX enable in AXI stream BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 20:44:43 -07:00 |
|
Alex Forencich
|
159c9d6241
|
eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 16:11:07 -07:00 |
|
Alex Forencich
|
76d4465081
|
eth: Convert UltraScale wrapper to use unpacked arrays for channels
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 16:10:37 -07:00 |
|
Alex Forencich
|
a74a49cffb
|
xfcp: Add XFCP module for APB
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 21:01:17 -07:00 |
|
Alex Forencich
|
86f52189b5
|
xfcp: Symlinks for common testbench code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 20:59:58 -07:00 |
|
Alex Forencich
|
8f5a534d35
|
axi: Tie off ruser/buser in AXI lite RAM modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 16:30:32 -07:00 |
|
Alex Forencich
|
bdfc0f120c
|
axi: Tie off ruser/buser in AXI RAM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 16:28:59 -07:00 |
|
Alex Forencich
|
88018ac9e8
|
axi: Add AXI lite to APB adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 16:14:17 -07:00 |
|
Alex Forencich
|
952232ad66
|
apb: Add APB dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 15:25:21 -07:00 |
|
Alex Forencich
|
f25e41de18
|
apb: Add APB RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 15:24:56 -07:00 |
|
Alex Forencich
|
f4f473afeb
|
apb: Add user sideband signals to APB interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 15:19:07 -07:00 |
|
Alex Forencich
|
e836357c33
|
ci: Update packages
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-30 14:38:49 -07:00 |
|
Alex Forencich
|
38ae0c1587
|
eth: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 15:18:23 -07:00 |
|
Alex Forencich
|
9307e0df6c
|
pcie: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 15:17:46 -07:00 |
|
Alex Forencich
|
1e12094f45
|
stats: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 14:58:16 -07:00 |
|
Alex Forencich
|
32ed95893c
|
dma: Clean up casts in DMA PSDPRAM model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 14:37:41 -07:00 |
|
Alex Forencich
|
e42a2dd8b4
|
lss: Use cocotb.start_soon instead of cocotb.fork
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 14:36:27 -07:00 |
|
Alex Forencich
|
6a5faf9ebf
|
Cast to int instead of using .integer
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 11:25:34 -07:00 |
|
Alex Forencich
|
40908b1b92
|
Testbench cleanup for cocotb 2.0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 10:59:38 -07:00 |
|
Alex Forencich
|
884fe1a006
|
apb: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-06 16:50:44 -07:00 |
|
Alex Forencich
|
81a918d223
|
apb: Add SV interface for APB
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-06 16:50:38 -07:00 |
|
Alex Forencich
|
20f14ace97
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-06 07:06:50 -07:00 |
|
Alex Forencich
|
553dea534e
|
eth/example/HTG_ZRF8: Add example design for HTG-ZRF8-EM and HTG-ZRF8-R2
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-06 07:03:35 -07:00 |
|
Alex Forencich
|
0d7e0cf590
|
eth/example/ZCU111: Clean up RFDC clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-05 07:30:30 -07:00 |
|
Alex Forencich
|
6c9026bccf
|
eth/example/HTG9200: Fix refclock frequency in testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-05 07:15:26 -07:00 |
|
Alex Forencich
|
2ae5b5fae3
|
pcie: Remove TLP_HDR_W parameter from testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-01 22:08:18 -07:00 |
|
Alex Forencich
|
cdfb1566f5
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:38:06 -07:00 |
|
Alex Forencich
|
a6db298eeb
|
dma: Add async DMA PSDPRAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:30:25 -07:00 |
|
Alex Forencich
|
48da5315fe
|
dma: Add DMA PSDPRAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:29:55 -07:00 |
|
Alex Forencich
|
d57b49b29c
|
dma: Add PSDPRAM simulation model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:05:20 -07:00 |
|
Alex Forencich
|
c5fea4d920
|
dma: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:04:44 -07:00 |
|
Alex Forencich
|
10500e6c6c
|
dma: Add DMA RAM interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:04:22 -07:00 |
|
Alex Forencich
|
e87e16c299
|
axi: Add AXI FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 22:17:53 -07:00 |
|
Alex Forencich
|
0080125120
|
axi: Add AXI to AXI lite adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 21:11:20 -07:00 |
|
Alex Forencich
|
94a821192c
|
axi: Add AXI width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 21:10:08 -07:00 |
|