Alex Forencich
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328a00e30f
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lfsr: Add LFSR PRBS generator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 15:28:08 -08:00 |
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Alex Forencich
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fb69371974
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lfsr: Add LFSR CRC computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-05 15:27:44 -08:00 |
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Alex Forencich
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e35d2b2c03
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eth: Add 10G PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 17:10:21 -08:00 |
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Alex Forencich
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c6ea4071eb
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eth: Add XGMII/BASE-R encode/decode modules and testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 16:14:32 -08:00 |
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Alex Forencich
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8ee1f5cd18
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lfsr: Add parametrizable LFSR module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 15:39:33 -08:00 |
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Alex Forencich
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f0c9f69987
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axis: Add COBS encoder module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 11:49:50 -08:00 |
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Alex Forencich
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215732b309
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axis: Work around verilator linter bug in AXI stream FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 11:40:14 -08:00 |
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Alex Forencich
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9138a7a51e
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axis: Add COBS decoder module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 11:39:38 -08:00 |
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Alex Forencich
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85eb59f747
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axis: Add AXI stream broadcaster module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 10:38:15 -08:00 |
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Alex Forencich
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beb36b78e0
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io: Add switch debounce module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-04 00:16:34 -08:00 |
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Alex Forencich
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6ba257aa10
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sync: Add signal synchronizer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:43:18 -08:00 |
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Alex Forencich
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9cc4cbc670
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sync: Add reset synchronizer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:42:47 -08:00 |
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Alex Forencich
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e23627c92f
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axis: Add AXI stream combined FIFO/adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:34:34 -08:00 |
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Alex Forencich
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c0a164a1d2
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axis: Add AXI stream adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:33:29 -08:00 |
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Alex Forencich
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03c0883356
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axis: Add AXI stream FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 22:43:17 -08:00 |
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Alex Forencich
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9590811570
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axis: Add AXI stream pipeline FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 16:35:52 -08:00 |
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Alex Forencich
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47e4658b55
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axis: Add AXI stream pipeline register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 16:35:25 -08:00 |
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Alex Forencich
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c4558a02f0
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lss: Add UART module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 15:02:48 -08:00 |
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Alex Forencich
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c7f719b435
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axis: Add AXI stream register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 12:49:08 -08:00 |
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Alex Forencich
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e1233eaffe
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axis: Add SV interface for AXI stream
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-02 22:45:12 -08:00 |
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