Alex Forencich
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76d4465081
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eth: Convert UltraScale wrapper to use unpacked arrays for channels
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-02 16:10:37 -07:00 |
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Alex Forencich
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38ae0c1587
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eth: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 15:18:23 -07:00 |
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Alex Forencich
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6a5faf9ebf
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Cast to int instead of using .integer
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 11:25:34 -07:00 |
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Alex Forencich
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40908b1b92
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Testbench cleanup for cocotb 2.0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 10:59:38 -07:00 |
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Alex Forencich
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7031a3f0b1
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eth: Add 32-bit mode tests for UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-17 22:19:55 -07:00 |
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Alex Forencich
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5b0cae2aac
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eth: Add 32-bit support to combined MAC+PCS module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-17 21:37:34 -07:00 |
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Alex Forencich
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fd521a1511
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eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-17 20:15:50 -07:00 |
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Alex Forencich
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295dc2dd23
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eth: Add 32-bit AXI stream BASE-R RX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-17 20:15:09 -07:00 |
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Alex Forencich
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ebb8bf0bd4
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eth: Add 32-bit AXI stream BASE-R TX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-17 20:14:30 -07:00 |
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Alex Forencich
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6f5adb1b41
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eth: Reset pack_seq even if the header is not marked as valid
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-17 16:32:48 -07:00 |
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Alex Forencich
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6407b4c7f0
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eth: Support 32-bit sync gearbox in 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-15 13:11:26 -07:00 |
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Alex Forencich
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ab09ceb891
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eth: Support 32 bit mode in BASE-R PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-15 13:00:14 -07:00 |
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Alex Forencich
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e6b5cd6ecd
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eth: Support 32 bit mode in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-15 12:56:03 -07:00 |
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Alex Forencich
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65eef8b5e8
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eth: Parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 19:28:21 -07:00 |
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Alex Forencich
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eae4d67367
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eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 17:57:57 -07:00 |
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Alex Forencich
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e846e7f0cd
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eth: Add gearbox support to 64-bit 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 16:39:55 -07:00 |
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Alex Forencich
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28195390a2
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eth: Add GBX_CNT to taxi_xgmii_baser_enc_64 testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 16:35:04 -07:00 |
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Alex Forencich
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0fd4000f69
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eth: Support both split and combined MAC/PCS in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 14:31:14 -07:00 |
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Alex Forencich
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886aa65522
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eth: Add testbench for taxi_eth_mac_25g_us module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 10:34:43 -07:00 |
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Alex Forencich
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98d06954cc
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eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 10:28:53 -07:00 |
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Alex Forencich
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4e66dd0f98
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eth: Rename gearbox start signals to sync
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-12 15:45:07 -07:00 |
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Alex Forencich
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e4762b7a8c
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eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-30 21:14:54 -07:00 |
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Alex Forencich
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aa8f19bf3b
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eth: Reorganize clock enable in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-27 23:56:28 -07:00 |
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Alex Forencich
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9bce7f4165
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eth: Shorten header argument name in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-27 21:27:46 -07:00 |
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Alex Forencich
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66b53d98a2
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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-18 12:25:59 -07:00 |
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