Alex Forencich
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83c52e6744
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axi: Add AXI-lite tie modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 17:37:36 -08:00 |
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Alex Forencich
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dfe13db9f7
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axi: Sweep burst size in AXI interconnect tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 17:28:11 -08:00 |
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Alex Forencich
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008e06ff48
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dma: Cast RAM address width appropriately
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:53:15 -08:00 |
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Alex Forencich
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ec00c2323c
|
dma: Cast PCIe TLP tag width appropriately
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:22:29 -08:00 |
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Alex Forencich
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cb3538a0de
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dma: Add interface configuration checks to DMA PSDPRAM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:21:24 -08:00 |
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Alex Forencich
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cbe0fa730d
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dma: Add missing ASID signals to DMA descriptor interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:12:42 -08:00 |
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Alex Forencich
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7449dcfdc3
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eth/example: Use logging.getLogger instead of SimLog
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-17 21:34:06 -08:00 |
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Alex Forencich
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75d28d5adb
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eth: Clean up MGT pin connections in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-14 12:07:26 -08:00 |
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Alex Forencich
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729bf79427
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eth: Move link speed detection logic from MAC wrapper to PHY interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 21:27:03 -08:00 |
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Alex Forencich
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a919552914
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eth: Fix widths
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 18:07:13 -08:00 |
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Alex Forencich
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4fc8baea96
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eth: Update example designs for APB interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 18:06:33 -08:00 |
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Alex Forencich
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5e77efbfe3
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eth: Add APB register interface to US/US+ transceiver wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 14:15:20 -08:00 |
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Alex Forencich
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2391e4f366
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xfcp: Add taxi_xfcp_mod_apb.f
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 12:08:40 -08:00 |
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Alex Forencich
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18f67e3faa
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xfcp: Fix ID string
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 12:05:19 -08:00 |
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Alex Forencich
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e0f570ebed
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eth: Add I2C to KCU105 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 12:04:32 -08:00 |
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Alex Forencich
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2582f86a11
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eth: Move reset synchronizer to top-level of GT wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-13 00:02:55 -08:00 |
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Alex Forencich
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898623a358
|
Update gitignore
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 23:39:59 -08:00 |
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Alex Forencich
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af9696eb06
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apb: Add APB width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 23:05:12 -08:00 |
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Alex Forencich
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cee2ed2b31
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axi: Fix names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:55:39 -08:00 |
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Alex Forencich
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8e3de66295
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apb: Fix parameter name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:07:04 -08:00 |
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Alex Forencich
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bfafd5777e
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apb: Clean up address width handling in interconnect module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-12 22:02:42 -08:00 |
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Alex Forencich
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8c3709d917
|
axi: Clean up address width handling in interconnect modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-12 22:01:45 -08:00 |
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Alex Forencich
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dd4c639600
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axi: Remove extraneous code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:43:42 -08:00 |
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Alex Forencich
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f472fda1e4
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apb: Fix interface indexing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-12 21:42:39 -08:00 |
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Alex Forencich
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92baa34b54
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axi: Fix interface indexing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:42:12 -08:00 |
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Alex Forencich
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b4d958d477
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axis: Use bin2gray function in async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:05:38 -08:00 |
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Alex Forencich
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ee31bbf936
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axi: Minor cleanup in AXIL-APB adapter module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:04:59 -08:00 |
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Alex Forencich
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18794f33c9
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apb: Add APB interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-12 17:04:07 -08:00 |
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Alex Forencich
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32200d9009
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 23:23:47 -08:00 |
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Alex Forencich
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baa9822580
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ci: Update to verilator 5.038
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 22:55:32 -08:00 |
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Alex Forencich
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ccb024f8ce
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axi: Add AXI crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 22:33:31 -08:00 |
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Alex Forencich
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0a4da49c74
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axi: Makefile parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 20:31:24 -08:00 |
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Alex Forencich
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cbbad58efb
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axi: Fix sideband signal handling in AXI lite crossbar
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 17:31:44 -08:00 |
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Alex Forencich
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053c9368e9
|
axi: Add AXI lite crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 15:06:32 -08:00 |
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Alex Forencich
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d68d421694
|
axi: Dereference interface arrays in interconnect modules when extracting parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 14:32:50 -08:00 |
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Alex Forencich
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3d5a9efdb8
|
axi: Add AXI interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 12:40:07 -08:00 |
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Alex Forencich
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34dd338acf
|
axi: Add AXI lite interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 10:20:26 -08:00 |
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Alex Forencich
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3519abbee5
|
eth: Add support for 10GBASE-R to KC705 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-09 14:24:05 -08:00 |
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Alex Forencich
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4e256cfe37
|
eth: Add support for 7-series GTX transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-09 13:39:14 -08:00 |
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Alex Forencich
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44ebbbbc87
|
eth: KC705 cleanup, add I2C
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-09 13:37:10 -08:00 |
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Alex Forencich
|
6054f76a17
|
eth: Add Ethernet example design for NetFPGA SUME
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 19:46:20 -08:00 |
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Alex Forencich
|
4dbfc4d388
|
eth: Add Ethernet example design for VC709
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 16:06:12 -08:00 |
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Alex Forencich
|
2d061a76f2
|
eth: Add support for 7-series GTH transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 00:39:50 -08:00 |
|
Alex Forencich
|
32eed71e89
|
eth: Clean up MAC wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:26:12 -08:00 |
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Alex Forencich
|
1cd6275877
|
eth: Update ZCU111 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:24:00 -08:00 |
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Alex Forencich
|
1e8917affb
|
eth: Update KCU105 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:23:12 -08:00 |
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Alex Forencich
|
cae7053e78
|
eth: Update KC705 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:23:00 -08:00 |
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Alex Forencich
|
004246608e
|
Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 02:14:19 -08:00 |
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Alex Forencich
|
5f814e7da8
|
Clean up always blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 01:51:18 -08:00 |
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Alex Forencich
|
efc907e4c9
|
axis: Add assertions to FIFO modules for USER_EN settings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 17:58:33 -08:00 |
|