Alex Forencich
|
4682591ec3
|
eth: Update ZCU111 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 18:08:19 -08:00 |
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Alex Forencich
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3c40ce964b
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eth: Update AS02MC04 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 17:59:46 -08:00 |
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Alex Forencich
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40cc51d062
|
eth: Update ZCU106 example design testbench to test both 32-bit and 64-bit configurations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 15:37:49 -08:00 |
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Alex Forencich
|
7dbe595e5b
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eth: Update ADM-PCIE-9V3 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 15:36:49 -08:00 |
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Alex Forencich
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77313e1ed0
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eth: Add example design for Alibaba AS02MC04
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 14:35:33 -08:00 |
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Alex Forencich
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7ec62b6b47
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eth: Push CRC computation logic towards input in 64-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:34:27 -07:00 |
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Alex Forencich
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f6bfd0d097
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eth: Push CRC computation logic towards input in 64-bit XGMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:10:30 -07:00 |
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Alex Forencich
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ae53b5d286
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eth: Push CRC computation logic towards input in 32-bit XGMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 19:09:59 -07:00 |
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Alex Forencich
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adf10be684
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eth: Remove unused rxc regs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-05 18:12:50 -07:00 |
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Alex Forencich
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08879e80b8
|
eth: Mask off end of packet when lane swapped
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:12:20 -07:00 |
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Alex Forencich
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59a3d5f511
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eth: Normalize signal and register names in MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-05 18:11:27 -07:00 |
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Alex Forencich
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2810b72147
|
eth: Decoding is don't care with termination in lane 0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 21:59:20 -07:00 |
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Alex Forencich
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caeacadb78
|
eth: Clean up masking, lane 0 never needs to be masked
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 20:06:58 -07:00 |
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Alex Forencich
|
93ef0f970b
|
eth: Re-nest if statements for termination character handling in 10G RX logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 19:01:47 -07:00 |
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Alex Forencich
|
e395398666
|
eth: Rework input encoding in BASE-R RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 18:43:20 -07:00 |
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Alex Forencich
|
7e08164e8d
|
eth: Add term_first_cycle_reg to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 17:01:53 -07:00 |
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Alex Forencich
|
879b65cc70
|
eth: Normalize CRC register naming in 10G RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 15:54:49 -07:00 |
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Alex Forencich
|
d0d6747f88
|
eth: Merge lane swapping logic into BASE-R encode logic in 64-bit BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 11:47:21 -07:00 |
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Alex Forencich
|
0e2acbf482
|
eth: Fix 2D array declarations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-04 11:02:30 -07:00 |
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Alex Forencich
|
04df834708
|
eth: Optimize frame length enforcement logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 15:49:51 -07:00 |
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Alex Forencich
|
8257fdf09e
|
eth: Remove unused encodings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-03 13:47:52 -07:00 |
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Alex Forencich
|
f4e36bd081
|
eth: Optimize padding logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 23:08:11 -07:00 |
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Alex Forencich
|
7e629d934f
|
Fix TX enable in AXI stream BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 20:44:43 -07:00 |
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Alex Forencich
|
159c9d6241
|
eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 16:11:07 -07:00 |
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Alex Forencich
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76d4465081
|
eth: Convert UltraScale wrapper to use unpacked arrays for channels
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 16:10:37 -07:00 |
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Alex Forencich
|
38ae0c1587
|
eth: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 15:18:23 -07:00 |
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Alex Forencich
|
6a5faf9ebf
|
Cast to int instead of using .integer
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 11:25:34 -07:00 |
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Alex Forencich
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40908b1b92
|
Testbench cleanup for cocotb 2.0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 10:59:38 -07:00 |
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Alex Forencich
|
553dea534e
|
eth/example/HTG_ZRF8: Add example design for HTG-ZRF8-EM and HTG-ZRF8-R2
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-06 07:03:35 -07:00 |
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Alex Forencich
|
0d7e0cf590
|
eth/example/ZCU111: Clean up RFDC clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-05 07:30:30 -07:00 |
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Alex Forencich
|
6c9026bccf
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eth/example/HTG9200: Fix refclock frequency in testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-05 07:15:26 -07:00 |
|
Alex Forencich
|
07ae2ba989
|
eth: Add RFDC to ZCU111 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:26:14 -07:00 |
|
Alex Forencich
|
4c43b68f94
|
eth: Add 6QSFP FMC support to HTG9200 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 16:24:39 -07:00 |
|
Alex Forencich
|
cf0ec74849
|
eth: HTG9200 example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 06:37:14 -07:00 |
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Alex Forencich
|
d4089096ae
|
example: Add example design for HTG-9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:19:58 -07:00 |
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Alex Forencich
|
2065151c01
|
eth: Update 10G-only example designs to use 32-bit MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 23:19:30 -07:00 |
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Alex Forencich
|
7031a3f0b1
|
eth: Add 32-bit mode tests for UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 22:19:55 -07:00 |
|
Alex Forencich
|
5b0cae2aac
|
eth: Add 32-bit support to combined MAC+PCS module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:37:34 -07:00 |
|
Alex Forencich
|
7b1ae24d95
|
eth: Report framing and bad block errors in 32-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:34:42 -07:00 |
|
Alex Forencich
|
fd521a1511
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:50 -07:00 |
|
Alex Forencich
|
295dc2dd23
|
eth: Add 32-bit AXI stream BASE-R RX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:09 -07:00 |
|
Alex Forencich
|
ebb8bf0bd4
|
eth: Add 32-bit AXI stream BASE-R TX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:14:30 -07:00 |
|
Alex Forencich
|
6f5adb1b41
|
eth: Reset pack_seq even if the header is not marked as valid
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 16:32:48 -07:00 |
|
Alex Forencich
|
e8cea4c860
|
eth: Use for loop to reduce duplication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 11:50:29 -07:00 |
|
Alex Forencich
|
facdc5fe68
|
eth: Remove extraneous constants
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-16 16:01:12 -07:00 |
|
Alex Forencich
|
17e48c5f51
|
eth: Support 32-bit mode in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:16:58 -07:00 |
|
Alex Forencich
|
6407b4c7f0
|
eth: Support 32-bit sync gearbox in 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:11:26 -07:00 |
|
Alex Forencich
|
ab09ceb891
|
eth: Support 32 bit mode in BASE-R PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:00:14 -07:00 |
|
Alex Forencich
|
e6b5cd6ecd
|
eth: Support 32 bit mode in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:56:03 -07:00 |
|
Alex Forencich
|
70c0e3d52a
|
eth: Fix RX BER monitor when gearbox is enabled
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:54:01 -07:00 |
|