Alex Forencich
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b3441f6408
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pcie: Rename enable to en in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-29 17:59:33 -07:00 |
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Alex Forencich
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63c961cab4
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pcie: Fix some corner cases in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-29 16:50:31 -07:00 |
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Alex Forencich
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b5c9c02b03
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pcie: Add UltraScale PCIe AXI Lite Master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-25 22:39:28 -07:00 |
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Alex Forencich
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06e6f3e1b4
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lss: Optimize delay implementation in I2C master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-24 11:30:03 -07:00 |
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Alex Forencich
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c2c4f5316d
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xfcp: Fix width
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-24 11:26:25 -07:00 |
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Alex Forencich
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07ae2ba989
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eth: Add RFDC to ZCU111 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:26:14 -07:00 |
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Alex Forencich
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4c43b68f94
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eth: Add 6QSFP FMC support to HTG9200 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 16:24:39 -07:00 |
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Alex Forencich
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cf0ec74849
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eth: HTG9200 example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-20 06:37:14 -07:00 |
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Alex Forencich
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5e890bc6cd
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axis: Add AXI stream tie and null source/sink modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 06:33:21 -07:00 |
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Alex Forencich
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a8dbe26f12
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zircon: tdest not used on TX path after length/checksum computation, which also extracts the tdest value
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-15 13:36:14 -07:00 |
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Alex Forencich
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3a07e3e28c
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zircon: Improve sideband signal handling in length/checksum computation module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-15 13:34:15 -07:00 |
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Alex Forencich
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d0efd5f24c
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zircon: Connect tdest
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-14 14:11:55 -07:00 |
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Alex Forencich
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9955b79fcd
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zircon: Add FIFO configuration parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-13 17:17:34 -07:00 |
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Alex Forencich
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af8daa89ce
|
zircon: Fix flow control bug in parser
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-13 13:44:49 -07:00 |
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Alex Forencich
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0aad8ef2cc
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zircon: Fix testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:33:05 -07:00 |
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Alex Forencich
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e5ce27cc30
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zircon: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:13:47 -07:00 |
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Alex Forencich
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67bfb947f4
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zircon: Add TX buffer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:09:04 -07:00 |
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Alex Forencich
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18fdf53d5d
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zircon: Add ingress and egress modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:08:40 -07:00 |
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Alex Forencich
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48465423fb
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zircon: Add length and checksum computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 15:06:12 -07:00 |
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Alex Forencich
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7c1f2652b6
|
zircon: Add TX deparser module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 14:57:14 -07:00 |
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Alex Forencich
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babce69bd0
|
zircon: Add RX parser module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-06 14:49:22 -07:00 |
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Alex Forencich
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65cb6124c4
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:20:34 -07:00 |
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Alex Forencich
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a16a667f81
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lss: Add I2C init module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:20:21 -07:00 |
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Alex Forencich
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d4089096ae
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example: Add example design for HTG-9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:19:58 -07:00 |
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Alex Forencich
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467b044e88
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lss: Add missing file list file handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 15:15:29 -07:00 |
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Alex Forencich
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89f60f26ff
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lss: Add some interface configuration checks to I2C modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 14:40:56 -07:00 |
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Alex Forencich
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8017534c45
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lss: Rename I2C data ports to reduce ambiguity
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 14:40:33 -07:00 |
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Alex Forencich
|
4620370035
|
lss: Add I2C slave AXI lite master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 00:44:14 -07:00 |
|
Alex Forencich
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37825a02f4
|
lss: Add I2C slave module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 00:22:11 -07:00 |
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Alex Forencich
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8bcd7ca037
|
axis: Expand size range for concatenator module tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-31 14:13:13 -07:00 |
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Alex Forencich
|
933899887a
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axis: Add AXI stream switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-31 11:47:49 -07:00 |
|
Alex Forencich
|
dd8b2a89ed
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axis: Remove unnecessary idle cycles in taxi_axis_concat
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 22:03:16 -07:00 |
|
Alex Forencich
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bd0b0cd75a
|
Update documentation URL
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 19:12:45 -07:00 |
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Alex Forencich
|
d10e3cf5c0
|
axis: Add AXI stream demultiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 19:10:48 -07:00 |
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Alex Forencich
|
b266aa2949
|
axis: Add AXI stream concatenator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-30 18:57:11 -07:00 |
|
Alex Forencich
|
059c7cd5ce
|
axis: Minor cleanup in taxi_axis_mux
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-29 09:43:11 -07:00 |
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Alex Forencich
|
75a8750679
|
axis: Minor cleanup in taxi_axis_arb_mux
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-07-29 09:40:03 -07:00 |
|
Alex Forencich
|
2065151c01
|
eth: Update 10G-only example designs to use 32-bit MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 23:19:30 -07:00 |
|
Alex Forencich
|
7031a3f0b1
|
eth: Add 32-bit mode tests for UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 22:19:55 -07:00 |
|
Alex Forencich
|
5b0cae2aac
|
eth: Add 32-bit support to combined MAC+PCS module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:37:34 -07:00 |
|
Alex Forencich
|
7b1ae24d95
|
eth: Report framing and bad block errors in 32-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:34:42 -07:00 |
|
Alex Forencich
|
fd521a1511
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:50 -07:00 |
|
Alex Forencich
|
295dc2dd23
|
eth: Add 32-bit AXI stream BASE-R RX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:09 -07:00 |
|
Alex Forencich
|
ebb8bf0bd4
|
eth: Add 32-bit AXI stream BASE-R TX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:14:30 -07:00 |
|
Alex Forencich
|
6f5adb1b41
|
eth: Reset pack_seq even if the header is not marked as valid
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 16:32:48 -07:00 |
|
Alex Forencich
|
e8cea4c860
|
eth: Use for loop to reduce duplication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 11:50:29 -07:00 |
|
Alex Forencich
|
facdc5fe68
|
eth: Remove extraneous constants
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-16 16:01:12 -07:00 |
|
Alex Forencich
|
17e48c5f51
|
eth: Support 32-bit mode in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:16:58 -07:00 |
|
Alex Forencich
|
6407b4c7f0
|
eth: Support 32-bit sync gearbox in 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:11:26 -07:00 |
|
Alex Forencich
|
ab09ceb891
|
eth: Support 32 bit mode in BASE-R PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:00:14 -07:00 |
|