Alex Forencich
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bef82674d3
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axi: Add AXI tie modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 17:37:43 -08:00 |
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Alex Forencich
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83c52e6744
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axi: Add AXI-lite tie modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 17:37:36 -08:00 |
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Alex Forencich
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cee2ed2b31
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axi: Fix names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:55:39 -08:00 |
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Alex Forencich
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8c3709d917
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axi: Clean up address width handling in interconnect modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:01:45 -08:00 |
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Alex Forencich
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dd4c639600
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axi: Remove extraneous code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:43:42 -08:00 |
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Alex Forencich
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92baa34b54
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axi: Fix interface indexing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:42:12 -08:00 |
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Alex Forencich
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ee31bbf936
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axi: Minor cleanup in AXIL-APB adapter module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:04:59 -08:00 |
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Alex Forencich
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ccb024f8ce
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axi: Add AXI crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 22:33:31 -08:00 |
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Alex Forencich
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cbbad58efb
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axi: Fix sideband signal handling in AXI lite crossbar
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 17:31:44 -08:00 |
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Alex Forencich
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053c9368e9
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axi: Add AXI lite crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 15:06:32 -08:00 |
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Alex Forencich
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d68d421694
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axi: Dereference interface arrays in interconnect modules when extracting parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 14:32:50 -08:00 |
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Alex Forencich
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3d5a9efdb8
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axi: Add AXI interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 12:40:07 -08:00 |
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Alex Forencich
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34dd338acf
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axi: Add AXI lite interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 10:20:26 -08:00 |
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Alex Forencich
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004246608e
|
Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 02:14:19 -08:00 |
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Alex Forencich
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5f814e7da8
|
Clean up always blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 01:51:18 -08:00 |
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Alex Forencich
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8f5a534d35
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axi: Tie off ruser/buser in AXI lite RAM modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-30 16:30:32 -07:00 |
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Alex Forencich
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bdfc0f120c
|
axi: Tie off ruser/buser in AXI RAM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-30 16:28:59 -07:00 |
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Alex Forencich
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88018ac9e8
|
axi: Add AXI lite to APB adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-30 16:14:17 -07:00 |
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Alex Forencich
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e87e16c299
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axi: Add AXI FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 22:17:53 -07:00 |
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Alex Forencich
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0080125120
|
axi: Add AXI to AXI lite adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 21:11:20 -07:00 |
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Alex Forencich
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94a821192c
|
axi: Add AXI width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 21:10:08 -07:00 |
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Alex Forencich
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5f6487964e
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axi: Add MAX_BURST_LEN and NARROW_BURST_EN parameters to AXI interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 13:55:33 -07:00 |
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Alex Forencich
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e43d6acbbd
|
axi: Add AXI lite to AXI adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-30 13:40:43 -07:00 |
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Alex Forencich
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c22e659259
|
axi: Add AXI lite width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 13:02:27 -07:00 |
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Alex Forencich
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66b53d98a2
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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-18 12:25:59 -07:00 |
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