Alex Forencich
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f472fda1e4
|
apb: Fix interface indexing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:42:39 -08:00 |
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Alex Forencich
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92baa34b54
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axi: Fix interface indexing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:42:12 -08:00 |
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Alex Forencich
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b4d958d477
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axis: Use bin2gray function in async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:05:38 -08:00 |
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Alex Forencich
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ee31bbf936
|
axi: Minor cleanup in AXIL-APB adapter module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:04:59 -08:00 |
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Alex Forencich
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18794f33c9
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apb: Add APB interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:04:07 -08:00 |
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Alex Forencich
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32200d9009
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 23:23:47 -08:00 |
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Alex Forencich
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baa9822580
|
ci: Update to verilator 5.038
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 22:55:32 -08:00 |
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Alex Forencich
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ccb024f8ce
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axi: Add AXI crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 22:33:31 -08:00 |
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Alex Forencich
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0a4da49c74
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axi: Makefile parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 20:31:24 -08:00 |
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Alex Forencich
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cbbad58efb
|
axi: Fix sideband signal handling in AXI lite crossbar
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 17:31:44 -08:00 |
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Alex Forencich
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053c9368e9
|
axi: Add AXI lite crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 15:06:32 -08:00 |
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Alex Forencich
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d68d421694
|
axi: Dereference interface arrays in interconnect modules when extracting parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 14:32:50 -08:00 |
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Alex Forencich
|
3d5a9efdb8
|
axi: Add AXI interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 12:40:07 -08:00 |
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Alex Forencich
|
34dd338acf
|
axi: Add AXI lite interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-11 10:20:26 -08:00 |
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Alex Forencich
|
3519abbee5
|
eth: Add support for 10GBASE-R to KC705 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-09 14:24:05 -08:00 |
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Alex Forencich
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4e256cfe37
|
eth: Add support for 7-series GTX transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-09 13:39:14 -08:00 |
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Alex Forencich
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44ebbbbc87
|
eth: KC705 cleanup, add I2C
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-09 13:37:10 -08:00 |
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Alex Forencich
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6054f76a17
|
eth: Add Ethernet example design for NetFPGA SUME
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 19:46:20 -08:00 |
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Alex Forencich
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4dbfc4d388
|
eth: Add Ethernet example design for VC709
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 16:06:12 -08:00 |
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Alex Forencich
|
2d061a76f2
|
eth: Add support for 7-series GTH transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-08 00:39:50 -08:00 |
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Alex Forencich
|
32eed71e89
|
eth: Clean up MAC wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:26:12 -08:00 |
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Alex Forencich
|
1cd6275877
|
eth: Update ZCU111 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:24:00 -08:00 |
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Alex Forencich
|
1e8917affb
|
eth: Update KCU105 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:23:12 -08:00 |
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Alex Forencich
|
cae7053e78
|
eth: Update KC705 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 12:23:00 -08:00 |
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Alex Forencich
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004246608e
|
Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 02:14:19 -08:00 |
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Alex Forencich
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5f814e7da8
|
Clean up always blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 01:51:18 -08:00 |
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Alex Forencich
|
efc907e4c9
|
axis: Add assertions to FIFO modules for USER_EN settings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 17:58:33 -08:00 |
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Alex Forencich
|
9009880073
|
eth: Enable tuser signal in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 17:44:50 -08:00 |
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Alex Forencich
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434f31887e
|
eth: Use tie and null_src modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 09:35:26 -08:00 |
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Alex Forencich
|
c6eac348f6
|
eth: Update HTG-9200 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-06 00:49:50 -08:00 |
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Alex Forencich
|
0fe56c5390
|
eth: Update Alveo example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 23:42:03 -08:00 |
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Alex Forencich
|
b97eb139ca
|
eth: Update XUPP3R/XUSP3S example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 22:02:32 -08:00 |
|
Alex Forencich
|
66a93a734f
|
eth: Update HTG-ZRF8-EM/R2 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:54:04 -08:00 |
|
Alex Forencich
|
06eb4aafcd
|
eth: Update VCU118 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:51:40 -08:00 |
|
Alex Forencich
|
0f5bc4eba8
|
eth: Update VCU108 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:49:33 -08:00 |
|
Alex Forencich
|
31081b6a23
|
eth: Update fb2CG@KU15P example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:49:09 -08:00 |
|
Alex Forencich
|
c2858c183e
|
eth: Fix typo in fb2CG@KU15P example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 21:28:42 -08:00 |
|
Alex Forencich
|
a7b2db9c20
|
eth: Update Nexus K35-S/K3P-S example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 20:50:32 -08:00 |
|
Alex Forencich
|
ae05128b44
|
eth: Update Nexus K3P-Q example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 20:46:30 -08:00 |
|
Alex Forencich
|
4682591ec3
|
eth: Update ZCU111 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 18:08:19 -08:00 |
|
Alex Forencich
|
3c40ce964b
|
eth: Update AS02MC04 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 17:59:46 -08:00 |
|
Alex Forencich
|
40cc51d062
|
eth: Update ZCU106 example design testbench to test both 32-bit and 64-bit configurations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 15:37:49 -08:00 |
|
Alex Forencich
|
7dbe595e5b
|
eth: Update ADM-PCIE-9V3 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 15:36:49 -08:00 |
|
Alex Forencich
|
77313e1ed0
|
eth: Add example design for Alibaba AS02MC04
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-05 14:35:33 -08:00 |
|
Alex Forencich
|
3b95e2f279
|
dma: Remove unnecessary handshake condition
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 17:45:54 -08:00 |
|
Alex Forencich
|
b0dd91aa8d
|
dma: Add UltraScale PCIe DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 17:18:26 -08:00 |
|
Alex Forencich
|
14d988d1f2
|
dma: Add AXI DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-04 12:41:07 -08:00 |
|
Alex Forencich
|
851919f16f
|
dma: Add AXI stream sink DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 21:30:55 -08:00 |
|
Alex Forencich
|
5663572421
|
dma: Add AXI stream source DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 21:30:20 -08:00 |
|
Alex Forencich
|
5b0c83fc57
|
dma: Add AXI streaming DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 17:14:24 -08:00 |
|