Byron Lathi
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00e4c551c1
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Make full sim manual
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2023-11-18 21:12:18 -08:00 |
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Byron Lathi
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cad6e80081
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Merge branch '11-create-rtc' into 'master'
Resolve "Create RTC"
Closes #11
See merge request bslathi19/super6502!40
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2023-11-19 03:54:43 +00:00 |
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Byron Lathi
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19461536a2
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Merge branch 'master' into 48-reduce-sim-time-for-full-sim
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2023-11-18 17:42:59 -08:00 |
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Byron Lathi
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5433b4c6dc
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Merge from main
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2023-11-18 17:41:59 -08:00 |
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Byron Lathi
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da2675a3fe
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Reduce sim time for full sim
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2023-11-18 16:43:19 -08:00 |
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Byron Lathi
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1b78f51933
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Check all edge interrupts
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2023-11-18 15:00:44 -08:00 |
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Byron Lathi
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dea6227958
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Add irq code tb
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2023-11-18 13:55:29 -08:00 |
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Byron Lathi
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95b0e874cf
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Implement RTC
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2023-11-17 21:51:09 -08:00 |
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Byron Lathi
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27066a7ace
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Test interrupt priority
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2023-11-16 18:54:25 -08:00 |
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Byron Lathi
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b259d7f084
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Fix edge trigger, reorganize testbench
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2023-11-16 18:28:48 -08:00 |
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Byron Lathi
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5d4bad80a2
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Fix level triggered test, add to ci
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2023-11-16 08:14:58 -08:00 |
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Byron Lathi
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e163e9461f
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Fix makefile, fix how interrupts are triggered
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2023-11-15 18:46:18 -08:00 |
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Byron Lathi
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40c54e26c0
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Demonstrate basic interrupt functionality
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2023-11-15 08:42:02 -08:00 |
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Byron Lathi
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2b248db94f
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Add skeleton of interrupt controller
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2023-11-15 08:27:29 -08:00 |
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Byron Lathi
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0fe57c6ad5
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Add beginnings of interrupt controller
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2023-10-31 23:44:09 -07:00 |
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Byron Lathi
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b70b49eac8
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Up sim time
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2023-10-26 21:54:08 -07:00 |
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Byron Lathi
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cf8a5d782f
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Make kernel as part of full chip sim
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2023-10-26 21:25:26 -07:00 |
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Byron Lathi
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e3ae984177
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Upload filesystem image as well
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2023-10-26 20:40:00 -07:00 |
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Byron Lathi
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7f3696d36c
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Reduce sim time
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2023-10-26 20:11:35 -07:00 |
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Byron Lathi
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3a9c0fb73f
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run vvp unbuffered
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2023-10-25 22:47:22 -07:00 |
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Byron Lathi
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6f36d2fcc4
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Fix off by 1 error
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2023-10-25 20:39:55 -07:00 |
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Byron Lathi
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b6e3b79bda
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Change bootloader to actually use sectors per cluster
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2023-10-25 08:34:28 -07:00 |
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Byron Lathi
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e7e1eab4a4
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Try long test
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2023-10-23 18:54:51 -07:00 |
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Byron Lathi
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9d26265bb5
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Update to use new binary sd card image
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2023-10-22 16:45:41 -07:00 |
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Byron Lathi
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eb8ef5ba7a
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Reuse existing harness instead of copying
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2023-10-21 22:35:57 -07:00 |
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Byron Lathi
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5f863c9857
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Add code testbench
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2023-10-21 17:07:43 -07:00 |
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Byron Lathi
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ac5564d03d
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Add test program for mapper, fix reset bug
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2023-10-20 08:27:51 -07:00 |
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Byron Lathi
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5a8d15de94
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Refactor for FPGA synthesis
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2023-10-19 18:57:42 -07:00 |
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Byron Lathi
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03456607c9
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Route all addresses through mapper
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2023-10-19 18:34:39 -07:00 |
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Byron Lathi
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69e443d223
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Add mapped address output and test
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2023-10-18 08:54:23 -07:00 |
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Byron Lathi
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35d4ea968e
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Update testbench, fix off by 1
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2023-10-18 08:40:00 -07:00 |
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Byron Lathi
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e621d4047b
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Add mapper and testbench
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2023-10-16 23:45:33 -07:00 |
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Byron Lathi
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360eecf3ca
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Revert super6502 back to before mapper
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2023-10-15 21:48:03 -07:00 |
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Byron Lathi
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a7b7f4fe35
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Update build
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2023-10-15 21:27:11 -07:00 |
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Byron Lathi
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dc2154e2c2
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Fix fpga project config
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2023-10-15 21:07:15 -07:00 |
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Byron Lathi
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155e89240a
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Merge from master
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2023-10-15 18:58:25 -07:00 |
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Byron Lathi
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e768b245bd
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rework state machine
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2023-10-15 18:24:19 -07:00 |
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Byron Lathi
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362c9f140f
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Fix synthesis issue
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2023-10-15 13:52:55 -07:00 |
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Byron Lathi
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32f6c0f8d9
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Add jsr test
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2023-10-15 13:30:09 -07:00 |
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Byron Lathi
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afd8de92cc
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Fix sdram wrapper state machine
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2023-10-15 13:12:46 -07:00 |
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Byron Lathi
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673386f9f9
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Change clk_2 to clk_cpu
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2023-10-12 19:32:12 -07:00 |
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Byron Lathi
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d3ea5ed4d1
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Use udisksctl
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2023-10-11 00:59:41 -07:00 |
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Byron Lathi
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8e70e5a7c4
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Update verilog sd
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2023-10-10 21:40:24 -07:00 |
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Byron Lathi
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57efb41ae0
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Increase sim time, update verilog sd
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2023-10-10 21:39:10 -07:00 |
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Byron Lathi
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97622ac3bb
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Update verilog sd
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2023-10-09 23:32:55 -07:00 |
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Byron Lathi
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7bb2dd9a7f
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Update verilog sd
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2023-10-09 22:33:44 -07:00 |
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Byron Lathi
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67fa368319
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Update verilog sd
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2023-10-09 21:13:21 -07:00 |
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Byron Lathi
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fc13114e49
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Update verilog sd
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2023-10-09 21:07:36 -07:00 |
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Byron Lathi
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532364b8d2
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remove sd from regular sim
Figure out how to do this later
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2023-10-06 22:08:40 -07:00 |
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Byron Lathi
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fe72a4e9ea
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Remove dependency on file, since its created anyway
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2023-10-06 13:21:54 -07:00 |
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