Byron Lathi
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5f863c9857
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Add code testbench
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2023-10-21 17:07:43 -07:00 |
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Byron Lathi
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ac5564d03d
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Add test program for mapper, fix reset bug
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2023-10-20 08:27:51 -07:00 |
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Byron Lathi
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5a8d15de94
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Refactor for FPGA synthesis
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2023-10-19 18:57:42 -07:00 |
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Byron Lathi
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03456607c9
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Route all addresses through mapper
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2023-10-19 18:34:39 -07:00 |
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Byron Lathi
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69e443d223
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Add mapped address output and test
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2023-10-18 08:54:23 -07:00 |
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Byron Lathi
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35d4ea968e
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Update testbench, fix off by 1
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2023-10-18 08:40:00 -07:00 |
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Byron Lathi
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e621d4047b
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Add mapper and testbench
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2023-10-16 23:45:33 -07:00 |
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Byron Lathi
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360eecf3ca
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Revert super6502 back to before mapper
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2023-10-15 21:48:03 -07:00 |
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Byron Lathi
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a7b7f4fe35
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Update build
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2023-10-15 21:27:11 -07:00 |
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Byron Lathi
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dc2154e2c2
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Fix fpga project config
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2023-10-15 21:07:15 -07:00 |
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Byron Lathi
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155e89240a
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Merge from master
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2023-10-15 18:58:25 -07:00 |
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Byron Lathi
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e768b245bd
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rework state machine
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2023-10-15 18:24:19 -07:00 |
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Byron Lathi
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362c9f140f
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Fix synthesis issue
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2023-10-15 13:52:55 -07:00 |
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Byron Lathi
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32f6c0f8d9
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Add jsr test
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2023-10-15 13:30:09 -07:00 |
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Byron Lathi
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afd8de92cc
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Fix sdram wrapper state machine
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2023-10-15 13:12:46 -07:00 |
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Byron Lathi
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673386f9f9
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Change clk_2 to clk_cpu
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2023-10-12 19:32:12 -07:00 |
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Byron Lathi
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d3ea5ed4d1
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Use udisksctl
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2023-10-11 00:59:41 -07:00 |
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Byron Lathi
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8e70e5a7c4
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Update verilog sd
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2023-10-10 21:40:24 -07:00 |
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Byron Lathi
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57efb41ae0
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Increase sim time, update verilog sd
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2023-10-10 21:39:10 -07:00 |
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Byron Lathi
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97622ac3bb
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Update verilog sd
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2023-10-09 23:32:55 -07:00 |
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Byron Lathi
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7bb2dd9a7f
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Update verilog sd
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2023-10-09 22:33:44 -07:00 |
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Byron Lathi
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67fa368319
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Update verilog sd
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2023-10-09 21:13:21 -07:00 |
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Byron Lathi
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fc13114e49
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Update verilog sd
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2023-10-09 21:07:36 -07:00 |
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Byron Lathi
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532364b8d2
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remove sd from regular sim
Figure out how to do this later
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2023-10-06 22:08:40 -07:00 |
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Byron Lathi
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fe72a4e9ea
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Remove dependency on file, since its created anyway
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2023-10-06 13:21:54 -07:00 |
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Byron Lathi
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d27e442d5e
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Use REPO_TOP in script, call script from makefile
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2023-10-06 13:18:36 -07:00 |
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Byron Lathi
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a5ff9fb5da
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Update verilog sd
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2023-10-06 12:46:29 -07:00 |
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Byron Lathi
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a3e0ab0e1e
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Use 8 bit memory !! Will eat all your RAM!
Figure out a better way to load memories that doesn't immediately oom
you.
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2023-10-06 07:28:34 -07:00 |
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Byron Lathi
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2b98ad1522
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Increase sim time to get into sd block reads
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2023-10-04 22:50:55 -07:00 |
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Byron Lathi
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e6e3044f25
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update sd emulator
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2023-10-04 20:27:25 -07:00 |
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Byron Lathi
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6a684f62f8
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Remove another wait, update sd emulator
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2023-10-04 20:24:56 -07:00 |
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Byron Lathi
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019b9c8120
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Update sd, remove wait state
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2023-10-04 19:11:45 -07:00 |
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Byron Lathi
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c1f7b33dda
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Update sd card emu
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2023-10-03 23:08:56 -07:00 |
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Byron Lathi
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3a211faed7
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Don't have sd wait in simulation
need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim
also bro the sim is like 8000x slower than irl.
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2023-09-30 17:40:01 -07:00 |
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Byron Lathi
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cc32430f2a
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Refactor makefile, update verilog-sd-emulator
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2023-09-29 23:48:28 -07:00 |
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Byron Lathi
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913351efd4
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Add sd emulator as submodule
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2023-09-28 23:09:47 -07:00 |
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Byron Lathi
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62967aa88d
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Resolve "Add build check to CI"
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2023-09-29 05:14:52 +00:00 |
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Byron Lathi
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d5bb93f9c9
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Fix the bad commit
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2023-09-28 21:30:38 -07:00 |
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Byron Lathi
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d113498459
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Try a bad commit
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2023-09-28 21:28:39 -07:00 |
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Byron Lathi
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85f53816f9
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Remove unneeded CR
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2023-09-27 23:03:22 -07:00 |
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Byron Lathi
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4925354f53
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Fix uart status multiple drivers
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2023-09-27 23:02:53 -07:00 |
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Byron Lathi
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4d0abbb508
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Add sim uart
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2023-09-27 22:15:27 -07:00 |
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Byron Lathi
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9e19a1eb72
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Disable sdr debug, initialize uart status
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2023-09-27 21:14:09 -07:00 |
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Byron Lathi
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ec4c3bab86
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Update verilog-6502 bslathi19/verilog-6502@aaf4c084ef
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2023-09-26 23:15:22 -07:00 |
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Byron Lathi
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915188e8f1
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New test program that causes the error
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2023-09-26 18:23:01 -07:00 |
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Byron Lathi
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c2dd5d616b
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Gate rdy behind sdram_cs #28
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2023-09-25 23:45:23 -07:00 |
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Byron Lathi
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4ee21f23b6
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Up the sim time
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2023-09-25 19:13:06 -07:00 |
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Byron Lathi
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95e05292cc
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Fix clocks, define RTL_SIM
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2023-09-24 23:58:32 -07:00 |
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Byron Lathi
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be68b4c9f9
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Change sdrclk and sysclk to have aligned rising edges
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2023-09-24 14:53:38 -07:00 |
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Byron Lathi
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3fcfa4d3ac
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Add REPO_TOP env var
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2023-09-24 10:35:17 -07:00 |
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