Byron Lathi
4925354f53
Fix uart status multiple drivers
2023-09-27 23:02:53 -07:00
Byron Lathi
4d0abbb508
Add sim uart
2023-09-27 22:15:27 -07:00
Byron Lathi
9e19a1eb72
Disable sdr debug, initialize uart status
2023-09-27 21:14:09 -07:00
Byron Lathi
ec4c3bab86
Update verilog-6502 bslathi19/verilog-6502@aaf4c084ef
2023-09-26 23:15:22 -07:00
Byron Lathi
915188e8f1
New test program that causes the error
2023-09-26 18:23:01 -07:00
Byron Lathi
c2dd5d616b
Gate rdy behind sdram_cs #28
2023-09-25 23:45:23 -07:00
Byron Lathi
4ee21f23b6
Up the sim time
2023-09-25 19:13:06 -07:00
Byron Lathi
95e05292cc
Fix clocks, define RTL_SIM
2023-09-24 23:58:32 -07:00
Byron Lathi
be68b4c9f9
Change sdrclk and sysclk to have aligned rising edges
2023-09-24 14:53:38 -07:00
Byron Lathi
3fcfa4d3ac
Add REPO_TOP env var
2023-09-24 10:35:17 -07:00
Byron Lathi
9bd031e35e
Add support for test programs
2023-09-24 10:29:32 -07:00
Byron Lathi
13ea5ca71b
Add memory
2023-09-24 10:06:23 -07:00
Byron Lathi
d3aa195adf
Add updated sim cpu with fix
2023-09-23 10:49:44 -07:00
Byron Lathi
00173f4e89
Add submodule back
2023-09-23 09:59:39 -07:00
Byron Lathi
77dd4f1002
remove sim submodule
2023-09-23 09:59:09 -07:00
Byron Lathi
bc0ab7eb54
Fix infinite loop
2023-09-22 19:46:25 -07:00
Byron Lathi
5e03795c09
Get something simulated
...
Infinite loop being caused somewhere
2023-09-21 23:22:17 -07:00
Byron Lathi
1f503b2d80
update sim environment
2023-09-21 20:35:52 -07:00
Byron Lathi
e50203dd3e
Add generic SDR
2023-09-21 19:23:31 -07:00
Byron Lathi
d37e32ec64
Add sim cpu
2023-09-18 23:27:54 -07:00
Byron Lathi
76aea3180a
Move mapper into src folder
2023-09-18 23:00:27 -07:00
Byron Lathi
66bebf476e
Merge from master
2023-09-18 20:08:59 -07:00
Byron Lathi
c466c62969
Resolve "Organize Project Better"
2023-09-19 02:57:26 +00:00
Byron Lathi
02ac7d5213
Add diagram, throw some code together
2023-09-07 23:41:17 -07:00
Byron Lathi
5fc71567f2
Add basic mapping
2023-09-06 20:18:36 -07:00
Byron Lathi
18140b32a0
Add null mapper
2023-09-06 19:48:51 -07:00
Byron Lathi
791bffb248
Add copy data back
2023-09-04 14:08:52 -07:00
Byron Lathi
15b7d50a30
Fix zerobss bug
...
Well, not really fix but problem is avoided for now
2023-09-01 21:49:36 -07:00
Byron Lathi
b2b3b84bc4
Kernel crashing
2023-08-26 23:15:36 +00:00
Byron Lathi
eba24c2990
Disable inits which fail
2023-08-26 13:42:06 -07:00
Byron Lathi
0247565f49
Get super simple kernel code running
2023-08-26 13:09:02 -07:00
Byron Lathi
d2700a64fb
Read entire file into memory
2023-08-26 08:10:20 -07:00
Byron Lathi
a971e7a717
Start reading options
2023-08-25 20:03:03 -07:00
Byron Lathi
21b456067a
Read text and data offset/length
2023-08-25 19:22:21 -07:00
Byron Lathi
8bccfed867
Change segment order to make o65 layout valid
...
VECTORS was messing things up
2023-08-22 20:49:07 -07:00
Byron Lathi
906516c4b5
Add comments and use less magic
2023-08-15 23:06:10 -07:00
Byron Lathi
68ff523b10
Use actual values from sd card
2023-08-15 19:30:11 -07:00
Byron Lathi
053b0d7e3e
Find bootloader in FAT
2023-08-12 19:03:24 -07:00
Byron Lathi
fd9389268a
Load root directory from sd card
2023-08-12 16:09:03 -07:00
Byron Lathi
6b0caea84c
Link bootloader with bios to get access to symbols
...
By doing this we don't need to call bios functions, we can just jsr
directly to the addresses. This does mean that everytime the bios
changes the bootloader has to change, but ideally all the bootloader
does is load the bios and then get remapped out of memory. Any important
drivers like file system can be loaded from the bootloader.
This also means that the runtime functions are located in the bios for
the bootloader, so the rom will have to stay mapped in until the kernel
is started, at which point it will have its own runtime and the rom and
bootloader are no longer needed.
2023-08-08 22:16:42 -07:00
Byron Lathi
e73c4e1d08
Rewrite readblock in assembly
2023-08-08 19:28:10 -07:00
Byron Lathi
446f4e7539
Get bios calls starting to work
2023-08-06 21:41:15 -07:00
Byron Lathi
709c60cf36
SD_command assembly rewrite
2023-07-23 16:25:13 -07:00
Byron Lathi
5ca5fca29b
Get SD card working in SPI
2023-07-23 14:55:14 -07:00
Byron Lathi
6a1a76db35
Implement basic SPI controller
2023-07-21 23:01:37 -07:00
Byron Lathi
85f12c75f1
Start spi controller and tb
2023-07-21 22:10:39 -07:00
Byron Lathi
6eeecda368
Add wait states during refresh
2023-07-19 21:06:54 -07:00
Byron Lathi
21e3a477c1
Update IP
2023-07-19 21:06:20 -07:00
Byron Lathi
2f11808f11
Change to simpler rom
2023-01-13 13:07:13 -06:00
Byron Lathi
7682dffe3c
Change test program to use correct args
...
Seems to work, when you run the test program it resets the card and
sends the voltage and test pattern, and it does receive a response from
the card.
2023-01-12 21:45:13 -06:00
