Commit Graph

511 Commits

Author SHA1 Message Date
Byron Lathi
e6a16b0c73 Add device setup test using kernel drivers 2023-11-20 08:29:35 -08:00
Byron Lathi
1811457b0f Merge branch '9-initialize-the-devices' into 'master'
Resolve "Initialize the devices"

Closes #9

See merge request bslathi19/super6502!46
2023-11-20 15:56:54 +00:00
Byron Lathi
3861e44693 PIC: Disable all irqs at start 2023-11-19 23:30:02 -08:00
Byron Lathi
1e9be6c764 RTC: Fix threshold/irq_threshold initialization
Also throw some newlines in the kernel print messages.
2023-11-19 23:28:11 -08:00
Byron Lathi
680bccee62 Init rtc and pic in kernel 2023-11-19 22:11:29 -08:00
Byron Lathi
7f01b79abf Add pic docs 2023-11-19 22:09:45 -08:00
Byron Lathi
013f47fb3f Add rtc docs 2023-11-19 20:58:40 -08:00
Byron Lathi
bce8c1c641 Toolchain: Reduce jobs, add retries 2023-11-19 15:22:54 -08:00
Byron Lathi
e55564c94d Merge branch '49-verify-rtc' into 'master'
Resolve "Verify RTC"

Closes #49

See merge request bslathi19/super6502!45
2023-11-19 23:13:57 +00:00
Byron Lathi
cf3aebc9f3 Fix irq code tb now that interrupts are used 2023-11-19 15:10:48 -08:00
Byron Lathi
429be0276a Add rtc to efinix project 2023-11-19 15:04:41 -08:00
Byron Lathi
7c24389b10 Update RTC code test 2023-11-19 13:50:00 -08:00
Byron Lathi
7002aeebe6 Add rtc code test 2023-11-19 11:58:37 -08:00
Byron Lathi
77629b16ce Merge branch '50-full-chip-sims-should-be-optional-and-have-better-finish-conditions' into 'master'
Resolve "Full chip sims should be optional and have better finish conditions."

Closes #50

See merge request bslathi19/super6502!44
2023-11-19 05:17:15 +00:00
Byron Lathi
00e4c551c1 Make full sim manual 2023-11-18 21:12:18 -08:00
Byron Lathi
cad6e80081 Merge branch '11-create-rtc' into 'master'
Resolve "Create RTC"

Closes #11

See merge request bslathi19/super6502!40
2023-11-19 03:54:43 +00:00
Byron Lathi
a881a60cb0 Merge branch '47-add-license-and-readme' into 'master'
Resolve "Add license and readme"

Closes #47

See merge request bslathi19/super6502!43
2023-11-19 03:54:27 +00:00
Byron Lathi
d10afda1c4 Merge branch '48-reduce-sim-time-for-full-sim' into 'master'
Resolve "reduce sim time for full sim"

Closes #48

See merge request bslathi19/super6502!42
2023-11-19 02:49:11 +00:00
Byron Lathi
19461536a2 Merge branch 'master' into 48-reduce-sim-time-for-full-sim 2023-11-18 17:42:59 -08:00
Byron Lathi
64a1ffa2ac Merge branch 'master' into 47-add-license-and-readme 2023-11-18 17:42:35 -08:00
Byron Lathi
5433b4c6dc Merge from main 2023-11-18 17:41:59 -08:00
Byron Lathi
d8199a6438 Merge branch '10-interrupt-controller' into 'master'
Resolve "Interrupt Controller"

Closes #10

See merge request bslathi19/super6502!41
2023-11-19 01:24:21 +00:00
Byron Lathi
6a0b8ada11 Update README 2023-11-18 17:16:04 -08:00
Byron Lathi
b1ca451721 Add README 2023-11-18 17:14:51 -08:00
Byron Lathi
287d81393a Add LICENSE 2023-11-19 00:48:32 +00:00
Byron Lathi
da2675a3fe Reduce sim time for full sim 2023-11-18 16:43:19 -08:00
Byron Lathi
21927e527b Add toolchain dependency to sim 2023-11-18 15:09:33 -08:00
Byron Lathi
1b78f51933 Check all edge interrupts 2023-11-18 15:00:44 -08:00
Byron Lathi
dea6227958 Add irq code tb 2023-11-18 13:55:29 -08:00
Byron Lathi
95b0e874cf Implement RTC 2023-11-17 21:51:09 -08:00
Byron Lathi
27a0fe5e69 Merge branch '10-interrupt-controller' into 'master'
Resolve "Interrupt Controller"

Closes #10

See merge request bslathi19/super6502!39
2023-11-17 16:00:14 +00:00
Byron Lathi
27066a7ace Test interrupt priority 2023-11-16 18:54:25 -08:00
Byron Lathi
b259d7f084 Fix edge trigger, reorganize testbench 2023-11-16 18:28:48 -08:00
Byron Lathi
5d4bad80a2 Fix level triggered test, add to ci 2023-11-16 08:14:58 -08:00
Byron Lathi
e163e9461f Fix makefile, fix how interrupts are triggered 2023-11-15 18:46:18 -08:00
Byron Lathi
40c54e26c0 Demonstrate basic interrupt functionality 2023-11-15 08:42:02 -08:00
Byron Lathi
2b248db94f Add skeleton of interrupt controller 2023-11-15 08:27:29 -08:00
Byron Lathi
0fe57c6ad5 Add beginnings of interrupt controller 2023-10-31 23:44:09 -07:00
Byron Lathi
e3ad299edf Update diagram again 2023-10-31 23:11:19 -07:00
Byron Lathi
646f34cbb6 Second diagram 2023-10-31 23:04:50 -07:00
Byron Lathi
ca9e792844 Add first design 2023-10-30 23:46:21 -07:00
Byron Lathi
ac5443c0a9 Merge branch 'long_sim' into 'master'
Long sim

See merge request bslathi19/super6502!38
2023-10-31 03:07:49 +00:00
Byron Lathi
e3662e703c Add back long string 2023-10-30 00:04:57 -07:00
Byron Lathi
876ae08cf3 Fix off by 1 in o65 option decoding 2023-10-29 21:38:04 -07:00
Byron Lathi
c6bf29649a Add some CLCs before ADCs 2023-10-29 19:47:15 -07:00
Byron Lathi
59a6f13eb3 Skip the copydata in kernel setup 2023-10-28 18:31:21 -07:00
Byron Lathi
2577ab2a9a Update kernel makefile, test more kernel code 2023-10-28 13:12:41 -07:00
Byron Lathi
4104a2eeb9 Do a more sane string print first 2023-10-27 20:49:06 -07:00
Byron Lathi
b70b49eac8 Up sim time 2023-10-26 21:54:08 -07:00
Byron Lathi
cf8a5d782f Make kernel as part of full chip sim 2023-10-26 21:25:26 -07:00