Alex Forencich
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b6be624bdb
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example/KCU105: Add support for 10GBASE-R on KCU105
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 23:15:24 -08:00 |
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Alex Forencich
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4a439783f1
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example/KR260: Add support for 10GBASE-R on KR260
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 23:01:52 -08:00 |
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Alex Forencich
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db8b1fc27e
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example/VCU108: Add 25G MACs on QSFP28 port on VCU108
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 22:33:54 -08:00 |
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Alex Forencich
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f0ec82a384
|
eth: Add MAC+PHY+GT wrapper for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 22:22:54 -08:00 |
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Alex Forencich
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7613cae4f0
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eth: Use 2D array for PFC config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 22:08:43 -08:00 |
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Alex Forencich
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7f2ecf9b49
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eth: Implement RX sequence error reporting in MAC+PHY module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 10:16:32 -08:00 |
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Alex Forencich
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422c54229e
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eth: Split block type checks in MAC+PHY to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 10:02:08 -08:00 |
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Alex Forencich
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8f6a99112b
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eth: Add missing block types to MAC+PHY logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 09:55:28 -08:00 |
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Alex Forencich
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6a294cef2c
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Use string type for string parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-21 19:14:28 -08:00 |
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Alex Forencich
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6154506c0a
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axis: Use reset synchronizer module in AXI stream async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-20 12:44:23 -08:00 |
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Alex Forencich
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17f3613ca4
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eth: Clean up function definitions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-20 12:21:33 -08:00 |
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Alex Forencich
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e388cb22c6
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example/KR260: Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-20 10:21:49 -08:00 |
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Alex Forencich
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650da9c972
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example/HTG940: Add example design for HTG940
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-20 10:20:15 -08:00 |
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Alex Forencich
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152b5aeed5
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example/KC705: Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-19 13:24:31 -08:00 |
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Alex Forencich
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4db3ee5cd5
|
example/KR260: Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-19 12:03:53 -08:00 |
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Alex Forencich
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a56a33abc9
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examples: Add notes on required licenses
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-19 12:02:07 -08:00 |
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Alex Forencich
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d5ed74431a
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example/KR260: Add example design for KR260
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-19 10:59:15 -08:00 |
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Alex Forencich
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ae6f22e4da
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example/KCU105: Fix MMCM config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-18 20:10:25 -08:00 |
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Alex Forencich
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8241f33d47
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example/VCU108: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-18 18:13:10 -08:00 |
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Alex Forencich
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a4025a1ead
|
example/KC705: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-18 18:12:54 -08:00 |
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Alex Forencich
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2e35f5b5ff
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example/KCU105: Add example design for KCU105
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-18 18:08:25 -08:00 |
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Alex Forencich
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c7b79f9afb
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example/VCU108: Add example design for VCU108
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-18 15:14:36 -08:00 |
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Alex Forencich
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daa5ca38af
|
example/KC705: Fix MMCM notes
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-18 14:26:22 -08:00 |
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Alex Forencich
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53688afeb5
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example/KC705: Add example design for Xilinx KC705
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-18 09:45:36 -08:00 |
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Alex Forencich
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36ea9fb8d4
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example/Arty: Clean up Arty example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-18 00:55:08 -08:00 |
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Alex Forencich
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db183c7bdd
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Add test durations for pytest-split
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-17 18:10:01 -08:00 |
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Alex Forencich
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6577d016e5
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Run example design testbenches in CI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-17 00:26:06 -08:00 |
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Alex Forencich
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2c6fac0b9d
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-17 00:13:51 -08:00 |
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Alex Forencich
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dd2a0d1bf3
|
example: Add example design for Arty A7
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-17 00:13:06 -08:00 |
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Alex Forencich
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c6ca108392
|
eth: Clean up testbench clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:45:19 -08:00 |
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Alex Forencich
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689cd34739
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eth: Add additional Ethernet MAC-related timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:30:15 -08:00 |
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Alex Forencich
|
1112545d0a
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:22:43 -08:00 |
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Alex Forencich
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94dba88560
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eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:42 -08:00 |
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Alex Forencich
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255b26d2f2
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eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:22 -08:00 |
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Alex Forencich
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baa5f72a6c
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eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:16:54 -08:00 |
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Alex Forencich
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ffaf05f2d1
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eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:05:59 -08:00 |
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Alex Forencich
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fab49d1435
|
eth: Add RGMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:50:42 -08:00 |
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Alex Forencich
|
c0583aaff5
|
eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:37:12 -08:00 |
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Alex Forencich
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1dc5463f00
|
eth: Add GMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:34:49 -08:00 |
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Alex Forencich
|
175230eeaf
|
eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:46:31 -08:00 |
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Alex Forencich
|
af912cc849
|
eth: Add MII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:05:41 -08:00 |
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Alex Forencich
|
da7fe065cc
|
io: Rework generic ODDR implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 19:27:56 -08:00 |
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Alex Forencich
|
d01a90298c
|
eth: Use correct clock for TX completions in MAC + FIFO testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:59:18 -08:00 |
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Alex Forencich
|
5c8037093b
|
eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:06:41 -08:00 |
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Alex Forencich
|
e3d8ad8d36
|
io: Add source-synchronous IO modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 15:44:34 -08:00 |
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Alex Forencich
|
e18a2b3457
|
io: Add generic IDDR and ODDR modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 15:41:56 -08:00 |
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Alex Forencich
|
51d6919622
|
ptp: Add timing constraints for PTP components
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 11:29:57 -08:00 |
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Alex Forencich
|
d048a8d7c7
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:23:57 -08:00 |
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Alex Forencich
|
9ad43f3433
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:13:01 -08:00 |
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Alex Forencich
|
fc1e0efad7
|
ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:07:46 -08:00 |
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