Alex Forencich
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898623a358
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Update gitignore
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 23:39:59 -08:00 |
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Alex Forencich
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af9696eb06
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apb: Add APB width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 23:05:12 -08:00 |
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Alex Forencich
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cee2ed2b31
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axi: Fix names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:55:39 -08:00 |
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Alex Forencich
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8e3de66295
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apb: Fix parameter name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:07:04 -08:00 |
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Alex Forencich
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bfafd5777e
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apb: Clean up address width handling in interconnect module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:02:42 -08:00 |
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Alex Forencich
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8c3709d917
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axi: Clean up address width handling in interconnect modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 22:01:45 -08:00 |
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Alex Forencich
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dd4c639600
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axi: Remove extraneous code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:43:42 -08:00 |
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Alex Forencich
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f472fda1e4
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apb: Fix interface indexing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:42:39 -08:00 |
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Alex Forencich
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92baa34b54
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axi: Fix interface indexing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 21:42:12 -08:00 |
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Alex Forencich
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b4d958d477
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axis: Use bin2gray function in async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:05:38 -08:00 |
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Alex Forencich
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ee31bbf936
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axi: Minor cleanup in AXIL-APB adapter module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:04:59 -08:00 |
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Alex Forencich
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18794f33c9
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apb: Add APB interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-12 17:04:07 -08:00 |
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Alex Forencich
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32200d9009
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 23:23:47 -08:00 |
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Alex Forencich
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baa9822580
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ci: Update to verilator 5.038
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 22:55:32 -08:00 |
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Alex Forencich
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ccb024f8ce
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axi: Add AXI crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 22:33:31 -08:00 |
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Alex Forencich
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0a4da49c74
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axi: Makefile parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 20:31:24 -08:00 |
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Alex Forencich
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cbbad58efb
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axi: Fix sideband signal handling in AXI lite crossbar
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 17:31:44 -08:00 |
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Alex Forencich
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053c9368e9
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axi: Add AXI lite crossbar module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 15:06:32 -08:00 |
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Alex Forencich
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d68d421694
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axi: Dereference interface arrays in interconnect modules when extracting parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 14:32:50 -08:00 |
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Alex Forencich
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3d5a9efdb8
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axi: Add AXI interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 12:40:07 -08:00 |
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Alex Forencich
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34dd338acf
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axi: Add AXI lite interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-11 10:20:26 -08:00 |
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Alex Forencich
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3519abbee5
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eth: Add support for 10GBASE-R to KC705 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-09 14:24:05 -08:00 |
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Alex Forencich
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4e256cfe37
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eth: Add support for 7-series GTX transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-09 13:39:14 -08:00 |
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Alex Forencich
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44ebbbbc87
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eth: KC705 cleanup, add I2C
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-09 13:37:10 -08:00 |
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Alex Forencich
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6054f76a17
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eth: Add Ethernet example design for NetFPGA SUME
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-08 19:46:20 -08:00 |
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Alex Forencich
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4dbfc4d388
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eth: Add Ethernet example design for VC709
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-08 16:06:12 -08:00 |
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Alex Forencich
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2d061a76f2
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eth: Add support for 7-series GTH transceiver to 10G/25G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-08 00:39:50 -08:00 |
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Alex Forencich
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32eed71e89
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eth: Clean up MAC wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 12:26:12 -08:00 |
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Alex Forencich
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1cd6275877
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eth: Update ZCU111 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 12:24:00 -08:00 |
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Alex Forencich
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1e8917affb
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eth: Update KCU105 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 12:23:12 -08:00 |
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Alex Forencich
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cae7053e78
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eth: Update KC705 example XDC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 12:23:00 -08:00 |
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Alex Forencich
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004246608e
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Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 02:14:19 -08:00 |
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Alex Forencich
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5f814e7da8
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Clean up always blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 01:51:18 -08:00 |
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Alex Forencich
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efc907e4c9
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axis: Add assertions to FIFO modules for USER_EN settings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-06 17:58:33 -08:00 |
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Alex Forencich
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9009880073
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eth: Enable tuser signal in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-06 17:44:50 -08:00 |
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Alex Forencich
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434f31887e
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eth: Use tie and null_src modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-06 09:35:26 -08:00 |
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Alex Forencich
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c6eac348f6
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eth: Update HTG-9200 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-06 00:49:50 -08:00 |
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Alex Forencich
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0fe56c5390
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eth: Update Alveo example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 23:42:03 -08:00 |
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Alex Forencich
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b97eb139ca
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eth: Update XUPP3R/XUSP3S example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 22:02:32 -08:00 |
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Alex Forencich
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66a93a734f
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eth: Update HTG-ZRF8-EM/R2 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 21:54:04 -08:00 |
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Alex Forencich
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06eb4aafcd
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eth: Update VCU118 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 21:51:40 -08:00 |
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Alex Forencich
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0f5bc4eba8
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eth: Update VCU108 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 21:49:33 -08:00 |
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Alex Forencich
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31081b6a23
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eth: Update fb2CG@KU15P example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 21:49:09 -08:00 |
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Alex Forencich
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c2858c183e
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eth: Fix typo in fb2CG@KU15P example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 21:28:42 -08:00 |
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Alex Forencich
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a7b2db9c20
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eth: Update Nexus K35-S/K3P-S example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 20:50:32 -08:00 |
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Alex Forencich
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ae05128b44
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eth: Update Nexus K3P-Q example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 20:46:30 -08:00 |
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Alex Forencich
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4682591ec3
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eth: Update ZCU111 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 18:08:19 -08:00 |
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Alex Forencich
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3c40ce964b
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eth: Update AS02MC04 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 17:59:46 -08:00 |
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Alex Forencich
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40cc51d062
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eth: Update ZCU106 example design testbench to test both 32-bit and 64-bit configurations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 15:37:49 -08:00 |
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Alex Forencich
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7dbe595e5b
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eth: Update ADM-PCIE-9V3 example design to use 32-bit MACs at 10G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 15:36:49 -08:00 |
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