Alex Forencich
|
c69eb63a69
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:29:50 -07:00 |
|
Alex Forencich
|
a53d18b9d3
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_32
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:28:59 -07:00 |
|
Alex Forencich
|
f8890e4d80
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_tx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:03:26 -07:00 |
|
Alex Forencich
|
4fd3028f77
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:01:57 -07:00 |
|
Alex Forencich
|
6d31116596
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_32
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:00:34 -07:00 |
|
Alex Forencich
|
07e781e186
|
eth: Improve oversize frame tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 17:21:36 -07:00 |
|
Alex Forencich
|
1b28dc4b9a
|
eth: Check stats outputs in AXI stream GMII RX module testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 13:32:03 -07:00 |
|
Alex Forencich
|
b073fc8efb
|
eth: Check stats outputs in AXI stream GMII TX module testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 13:25:53 -07:00 |
|
Alex Forencich
|
0ef0bb3409
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_rx
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-06 00:17:31 -07:00 |
|
Alex Forencich
|
5582eddfa8
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_tx
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-05 22:15:39 -07:00 |
|
Alex Forencich
|
5b16933210
|
eth: Test more lengths to shift alignment
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-26 23:13:13 -07:00 |
|
Alex Forencich
|
bec324dc03
|
eth: Fix bugs in 10G MAC RX related to short IFGs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-26 23:03:57 -07:00 |
|
Alex Forencich
|
ed9e8ffab3
|
eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 11:05:58 -08:00 |
|
Alex Forencich
|
6e4988f010
|
eth: Fix PFC/LFC tests for 10G MAC+PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 10:41:49 -08:00 |
|
Alex Forencich
|
07d75f231a
|
eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:35:09 -08:00 |
|
Alex Forencich
|
7613cae4f0
|
eth: Use 2D array for PFC config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:08:43 -08:00 |
|
Alex Forencich
|
6a294cef2c
|
Use string type for string parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-21 19:14:28 -08:00 |
|
Alex Forencich
|
c6ca108392
|
eth: Clean up testbench clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:45:19 -08:00 |
|
Alex Forencich
|
94dba88560
|
eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:42 -08:00 |
|
Alex Forencich
|
255b26d2f2
|
eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:22 -08:00 |
|
Alex Forencich
|
baa5f72a6c
|
eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:16:54 -08:00 |
|
Alex Forencich
|
ffaf05f2d1
|
eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:05:59 -08:00 |
|
Alex Forencich
|
c0583aaff5
|
eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:37:12 -08:00 |
|
Alex Forencich
|
175230eeaf
|
eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:46:31 -08:00 |
|
Alex Forencich
|
d01a90298c
|
eth: Use correct clock for TX completions in MAC + FIFO testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:59:18 -08:00 |
|
Alex Forencich
|
5c8037093b
|
eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:06:41 -08:00 |
|
Alex Forencich
|
2abe774f8a
|
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:48:54 -08:00 |
|
Alex Forencich
|
90650aee69
|
eth: Add 10G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:47:54 -08:00 |
|
Alex Forencich
|
8a67eaa220
|
eth: Clean up testbench parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:35:18 -08:00 |
|
Alex Forencich
|
04b73e7ddf
|
eth: Add 1G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:12:57 -08:00 |
|
Alex Forencich
|
8f8572bdee
|
eth: Add taxi_axis_if to MAC file list files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 15:54:15 -08:00 |
|
Alex Forencich
|
2616e3f3e3
|
eth: Add 10G Ethernet combined MAC+PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:40:50 -08:00 |
|
Alex Forencich
|
0ddb89b18f
|
eth: Add 10G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:26:03 -08:00 |
|
Alex Forencich
|
fa73f9c1d5
|
eth: Add 1G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:25:48 -08:00 |
|
Alex Forencich
|
8d3d703656
|
eth: Add MAC control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 19:59:11 -08:00 |
|
Alex Forencich
|
96e348ac84
|
eth: Invert TX completion output control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 23:24:28 -08:00 |
|
Alex Forencich
|
1c381ce22e
|
eth: Enable tuser signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 22:23:03 -08:00 |
|
Alex Forencich
|
72dabc5a9a
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:23 -08:00 |
|
Alex Forencich
|
2af4e7af3e
|
eth: Add AXI stream 64-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:15 -08:00 |
|
Alex Forencich
|
a375eb342d
|
eth: Add AXI stream 32-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:06 -08:00 |
|
Alex Forencich
|
c914adf9f1
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:02:48 -08:00 |
|
Alex Forencich
|
e3f047d735
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:27:27 -08:00 |
|
Alex Forencich
|
f0f2a25943
|
eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:54 -08:00 |
|
Alex Forencich
|
8046a46680
|
eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:06 -08:00 |
|
Alex Forencich
|
3f501aaac9
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:12:58 -08:00 |
|
Alex Forencich
|
584f2a6542
|
eth: Add MAC pause control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 21:11:14 -08:00 |
|
Alex Forencich
|
e35d2b2c03
|
eth: Add 10G PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 17:10:21 -08:00 |
|
Alex Forencich
|
c6ea4071eb
|
eth: Add XGMII/BASE-R encode/decode modules and testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 16:14:32 -08:00 |
|