Alex Forencich
|
fa0cd921a3
|
eth: Add 100G configuration to HTG-ZRF8 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-11 14:38:29 -07:00 |
|
Alex Forencich
|
1d741faa1c
|
eth: Add 100G configuration to NT200A01/XT200A02 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-11 14:35:11 -07:00 |
|
Alex Forencich
|
8a9c3ae5c9
|
eth: Clean up parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-11 13:58:54 -07:00 |
|
Alex Forencich
|
fec5037340
|
eth: Add 100G configuration to fb2CG@KU15P example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-11 13:54:25 -07:00 |
|
Alex Forencich
|
876be04a06
|
eth: Add 100G configuration to ADM-PCIE-9V3 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-11 13:34:49 -07:00 |
|
Alex Forencich
|
b7b48ca89b
|
eth: Add 100G configuration to Alveo example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-11 13:28:29 -07:00 |
|
Alex Forencich
|
b5ff317bd5
|
eth: Add 100G configuration to XUPP3R/XUSP3S example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 23:44:22 -07:00 |
|
Alex Forencich
|
27f1cd5441
|
eth: Ensure secondary QPLL is not configured for a higher line rate than the primary QPLL to prevent issues with timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 23:36:52 -07:00 |
|
Alex Forencich
|
f4e518ade6
|
eth: CMAC constraint cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 22:17:06 -07:00 |
|
Alex Forencich
|
fc61c78aa5
|
eth: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 21:03:02 -07:00 |
|
Alex Forencich
|
4b779732ec
|
eth: Add some notes to HTG-9200 constraints files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 21:02:14 -07:00 |
|
Alex Forencich
|
ad7bf4c9ce
|
eth: Fix GT bank and site annotations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 14:48:53 -07:00 |
|
Alex Forencich
|
e24e4345d7
|
eth: Add 100G configuration to HTG-9200 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 14:48:06 -07:00 |
|
Alex Forencich
|
b5bd7b163f
|
eth: Fix CMAC location constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 01:15:45 -07:00 |
|
Alex Forencich
|
3eb6677d20
|
eth: Add 100G configuration to VCU118 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 01:15:18 -07:00 |
|
Alex Forencich
|
0d3c6c5c5b
|
eth: Test 100G variant in VCU108 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 00:33:08 -07:00 |
|
Alex Forencich
|
c525b28931
|
eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 00:03:53 -07:00 |
|
Alex Forencich
|
31560de907
|
eth: Clean up 100G wrapper parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-10 00:03:30 -07:00 |
|
Alex Forencich
|
2eab7c402d
|
eth: Add 100G configuration to VCU108 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 22:33:53 -07:00 |
|
Alex Forencich
|
9436322bee
|
eth: Support UltraScale CMACE3 in 100G wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 21:48:14 -07:00 |
|
Alex Forencich
|
514972a66a
|
eth: Rename TCL script for CMACE4
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 20:51:07 -07:00 |
|
Alex Forencich
|
ac4584f545
|
eth: Add 100G configuration to RK-XCKU5P-F example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 18:43:01 -07:00 |
|
Alex Forencich
|
6abdba4fca
|
eth: Update 100G wrapper parametrization and simulation support
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 18:23:07 -07:00 |
|
Alex Forencich
|
ec6723e90d
|
eth: Consolidate example design testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 14:34:18 -07:00 |
|
Alex Forencich
|
ecc1558ab7
|
eth: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 12:34:41 -07:00 |
|
Alex Forencich
|
a3050e80bf
|
eth: Add 1000BASE-X support to AS02MC04 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-09 12:33:53 -07:00 |
|
Alex Forencich
|
511b65e4a5
|
eth: Update KR260 1000BASE-X example design implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-08 22:15:35 -07:00 |
|
Alex Forencich
|
dbb561497f
|
eth: Add 1G support to XEM8320 example
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-08 16:18:49 -07:00 |
|
Alex Forencich
|
6fe06100a7
|
eth: Remove redundant SFP_RATE parameter in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-08 16:09:36 -07:00 |
|
Alex Forencich
|
ed626fff67
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-08 00:50:21 -07:00 |
|
Alex Forencich
|
24ad4c970f
|
eth: Update CMAC wrapper clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-08 00:35:50 -07:00 |
|
Alex Forencich
|
ded4f94a0e
|
eth: Update wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-07 23:22:31 -07:00 |
|
Alex Forencich
|
89bb672524
|
hip: Integrate usrclk active logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-07 23:20:27 -07:00 |
|
Alex Forencich
|
7132d1817a
|
eth: Add 100G CMAC wrapper for US/US+
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-07 15:54:30 -07:00 |
|
Alex Forencich
|
d5d38c268e
|
eth: USXGMII is only supported in combined MAC/PCS logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-04 17:44:40 -07:00 |
|
Alex Forencich
|
e7fd1b6c22
|
eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-04 17:40:45 -07:00 |
|
Alex Forencich
|
927d259b57
|
eth: Fix issues with framing error detection in 64-bit BASE-R RX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-04 17:18:19 -07:00 |
|
Alex Forencich
|
b434897069
|
eth: Update testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-04 14:10:05 -07:00 |
|
Alex Forencich
|
ce7524ec75
|
eth: Add support for USXGMII symbol replication to 64-bit AXIS/BASE-R decode module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-04 12:58:06 -07:00 |
|
Alex Forencich
|
c68c3a4157
|
eth: Rework 32-bit BASE-R RX internal sequencing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-02 00:40:16 -07:00 |
|
Alex Forencich
|
cd7901f9fa
|
eth: Clean up framing error detection in 64-bit BASE-R RX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-01 15:48:26 -07:00 |
|
Alex Forencich
|
0f11edc77f
|
eth: Report framing error for invalid block headers in 16-bit BASE-R RX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-01 15:47:03 -07:00 |
|
Alex Forencich
|
a06edb43bb
|
eth: Fix IFG and DIC handling in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-01 14:26:55 -07:00 |
|
Alex Forencich
|
405d21faad
|
eth: Fix preamble for offset start in 64-bit BASE-R TX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-08-01 11:16:35 -07:00 |
|
Alex Forencich
|
f2db88022f
|
eth: Fix offset start in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-31 23:56:24 -07:00 |
|
Alex Forencich
|
75734d61b8
|
eth: Fix 64-bit USXGMII TX implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-31 23:23:57 -07:00 |
|
Alex Forencich
|
40f47d5748
|
eth: Warn on out-of-frame data transfers in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-31 23:23:14 -07:00 |
|
Alex Forencich
|
ba71a5815f
|
eth: Ensure repetition is disabled for USXGMII at full rate
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-29 00:25:03 -07:00 |
|
Alex Forencich
|
5ce621f5d6
|
eth: Add offset start tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-23 23:24:03 -07:00 |
|
Alex Forencich
|
5f378fad5a
|
eth: Reset match counts when transferring data
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-23 23:14:39 -07:00 |
|