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cdbb6a9720
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Get it to ACTUALLY compile :)
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2026-05-24 20:30:34 -07:00 |
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6c6c3d295b
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Add design doc
but I didn't really read it
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2026-05-24 20:09:02 -07:00 |
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a21cc4241a
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Get it to compile at least
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2026-05-24 20:06:08 -07:00 |
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151643b2ad
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Get it working more
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2026-05-24 17:13:20 -07:00 |
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61ee654b18
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Get it roughly working
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2026-05-24 15:53:50 -07:00 |
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aa8c4a64df
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First shot at happy path
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2026-05-22 23:54:33 -07:00 |
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df25550c8a
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Add cache arrays and test
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2026-05-22 22:27:53 -07:00 |
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3ea31e40aa
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Last commit before I nuke it
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2026-05-22 09:10:19 -07:00 |
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8fd83c2563
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Get it to kinda work
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2026-05-19 19:57:15 -07:00 |
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62a3408eb7
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Add some stuff related to cache
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2026-05-16 16:55:21 -07:00 |
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042d7724ff
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Move everything around
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2026-05-09 16:03:57 -07:00 |
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089df744aa
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32bit (#2)
Reviewed-on: #2
Co-authored-by: Byron Lathi <byron@byronlathi.com>
Co-committed-by: Byron Lathi <byron@byronlathi.com>
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2026-05-09 15:33:54 -07:00 |
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06f933fa56
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Factor out verilog-6502 submodule
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2026-04-18 18:55:05 -07:00 |
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db61ca2d74
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Create project
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2026-04-18 18:50:18 -07:00 |
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