Byron Lathi
6320af16ec
Update diagram to static ports
2024-08-15 22:51:41 -07:00
Byron Lathi
c4eba333e8
Add start of tcp docs
2024-08-05 20:32:07 -07:00
Byron Lathi
82f5238a15
Update sdspi with merged version
2024-07-31 22:08:02 -07:00
Byron Lathi
434fc1b28a
Fix sdspi, add missing source file
2024-07-31 22:02:47 -07:00
Byron Lathi
f99df72fe2
Update sdspi with write dma
2024-07-31 21:56:50 -07:00
Byron Lathi
e0f511df2e
Add new DMA files to project config
2024-07-26 23:02:40 -07:00
Byron Lathi
aa2e686b53
Update sdspi
2024-07-25 22:56:30 -07:00
Byron Lathi
5cd03a37eb
Start working on axi dma
2024-07-22 00:07:04 -07:00
Byron Lathi
90c5c0dc94
Update SD version and start working on DMA
2024-07-21 18:58:35 -07:00
Byron Lathi
abb1668f14
Synthesis file updates
2024-07-20 21:51:28 -07:00
Byron Lathi
3d05d07541
Move shadow to us, get some commands going
2024-07-20 21:40:26 -07:00
Byron Lathi
f6eeb80e25
switch to zipcpu sd sim
2024-07-20 18:11:32 -07:00
Byron Lathi
f126e383a3
Update SD stuff
2024-07-20 16:03:06 -07:00
Byron Lathi
bdb3fc96d6
Add new sd wrapper
...
Wrapper is neccesary for the address offset and also because the
controller will trigger on reads/writes to registers, but we need access
to each byte of the 32 bit registers.
The wrapper will need to somehow chose when to actually trigger the
controller, maybe by having shadow registers?
2024-07-17 21:18:13 -07:00
Byron Lathi
db630f2030
Update rtl-common, fix some axi violations in cpu writes
2024-07-17 20:31:36 -07:00
Byron Lathi
fa6f6505d4
Fixes for sim
2024-07-17 00:55:58 -07:00
Byron Lathi
63edbff30f
Reset renaming, set card_detect
2024-07-17 00:43:30 -07:00
Byron Lathi
6b7f7837dd
Use ZipCPU SD controller
...
I trust it more than the other one
2024-07-17 00:17:24 -07:00
Byron Lathi
e0bf1580b6
First pass at integrating sd controller
2024-07-16 18:57:57 -07:00
Byron Lathi
cdbf311fc1
Move controller and make wrapper folder
2024-07-16 00:28:48 -07:00
Byron Lathi
4f152623a0
Remove all traces of old sd controller
2024-07-16 00:03:13 -07:00
Byron Lathi
f04304bcbc
Add sd and wb2axi submodules
2024-07-15 23:58:53 -07:00
Byron Lathi
f5779922ef
Remove old SD controller
2024-07-14 22:20:28 -07:00
Byron Lathi
25f51deaa7
Synthesize sd card dma
2024-03-17 22:26:42 -07:00
Byron Lathi
9b50dab855
Update submodules, update sources
2024-03-15 21:02:53 -07:00
Byron Lathi
eb5c3b0b02
Update verilog sd to get up to cmd7
2024-03-14 19:34:04 -07:00
Byron Lathi
0f9e470d13
Update rtl common since I commited to the wrong branch (again)
2024-03-14 19:20:08 -07:00
Byron Lathi
4028c2a36e
Update rtl common since I commited to the wrong branch
2024-03-14 17:14:38 -07:00
Byron Lathi
335f877d66
Run simulation with verilog sd emulator
...
This also slowed the cpu clock down, we should speed it up again
2024-03-14 08:17:05 -07:00
Byron Lathi
24a7001aee
Add sd mode sd card emulator
2024-03-13 00:01:39 -07:00
Byron Lathi
262c4cfd83
Add sd emulator (need to add sd mode)
2024-03-12 22:14:02 -07:00
Byron Lathi
14cf303c9f
Update sd controller for sim
2024-03-12 21:51:55 -07:00
Byron Lathi
02097ff3b8
Update sd controller with data host
2024-03-12 20:23:41 -07:00
Byron Lathi
455814ec14
Update sd controller and test code
2024-03-12 18:20:51 -07:00
Byron Lathi
f7580f719f
Add program target to makefiles
2024-03-10 22:25:29 -07:00
Byron Lathi
61f6e53327
Updates based on fpga test
...
1. in SD mode, CMD0 does not have a response, so we specifically ignore
it.
2. The penable signal was messed up, although it looks like this doesn't
matter anyway
3. The SD clock should be out of phase from the data signal by 180
degrees, so that we get max hold time
2024-03-10 22:09:55 -07:00
Byron Lathi
3c0bf9740c
Delete init hex on clean
2024-03-10 21:56:48 -07:00
Byron Lathi
d3914b3a51
Add sd io pins
2024-03-10 16:09:12 -07:00
Byron Lathi
cb426670cd
Do synthesis with sd controller
2024-03-10 12:29:08 -07:00
Byron Lathi
da41e60ee7
integrate sd controller and super simple tb
2024-03-10 11:31:07 -07:00
Byron Lathi
81382925f8
Update rtl common and sd controller submodules
2024-03-10 10:24:50 -07:00
Byron Lathi
96e014567d
Add sd controller submodule
2024-03-04 00:06:29 -08:00
Byron Lathi
358dfdbe75
Add sdram io to fpga
2024-03-03 23:31:02 -08:00
Byron Lathi
aee04b777a
Fix sdram sim
...
Just need to add the RTL_SIM define
2024-03-03 21:33:28 -08:00
Byron Lathi
10a72d8e1f
Add sdram, don't think it works though
2024-03-03 20:43:37 -08:00
Byron Lathi
01b1ecbcac
Add basic sim
2024-03-03 17:09:17 -08:00
Byron Lathi
ab9da189d1
Build software correctly, ignore debugger files
2024-03-03 14:50:40 -08:00
Byron Lathi
42fbc17a2a
Add test code and top level Makefile
2024-03-03 12:52:44 -08:00
Byron Lathi
cd1dfa39cb
Fix PLL settings, add cpu output clock
2024-03-03 09:45:04 -08:00
Byron Lathi
0752220b0e
Add basic project with cpu, ram and rom
2024-03-02 22:46:48 -08:00
