Alex Forencich
|
93d9c8c9f6
|
eth: Add MAC statistics module to 10G MAC+PCS
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 12:18:42 -07:00 |
|
Alex Forencich
|
e90340db6e
|
eth: Add MAC statistics module to 1G MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-08 20:22:53 -07:00 |
|
Alex Forencich
|
bb90cd5a08
|
eth: Add MAC statistics module to 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-08 20:18:43 -07:00 |
|
Alex Forencich
|
3106fd5a96
|
eth: Add MAC statistics module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-08 10:49:45 -07:00 |
|
Alex Forencich
|
f920e56348
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_rx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:37:29 -07:00 |
|
Alex Forencich
|
c69eb63a69
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:29:50 -07:00 |
|
Alex Forencich
|
a53d18b9d3
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_32
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:28:59 -07:00 |
|
Alex Forencich
|
cb148ee905
|
eth: Report PHY-signalled errors as framing errors instead of bad blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:02:23 -07:00 |
|
Alex Forencich
|
f8890e4d80
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_tx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:03:26 -07:00 |
|
Alex Forencich
|
4fd3028f77
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:01:57 -07:00 |
|
Alex Forencich
|
6d31116596
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_32
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:00:34 -07:00 |
|
Alex Forencich
|
2e05b1eff2
|
eth: Fix RX byte statistics strobe on AXIS GMII RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 13:31:50 -07:00 |
|
Alex Forencich
|
bc023296f4
|
eth: Do not count SFD as payload data
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 13:25:39 -07:00 |
|
Alex Forencich
|
0ef0bb3409
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_rx
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-06 00:17:31 -07:00 |
|
Alex Forencich
|
5582eddfa8
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_tx
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-05 22:15:39 -07:00 |
|
Alex Forencich
|
df87998a1b
|
eth: Clean up error detection logic in combined MAC/PCS
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-27 09:33:56 -07:00 |
|
Alex Forencich
|
bec324dc03
|
eth: Fix bugs in 10G MAC RX related to short IFGs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-26 23:03:57 -07:00 |
|
Alex Forencich
|
75a3909c37
|
eth: Add default IFG setting to Ethernet MAC TX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-26 20:13:47 -07:00 |
|
Alex Forencich
|
ed9e8ffab3
|
eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 11:05:58 -08:00 |
|
Alex Forencich
|
181691941f
|
eth: Use signal sync module for RGMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:12:50 -08:00 |
|
Alex Forencich
|
f8d5d6a45e
|
eth: Use signal sync module for GMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:12:10 -08:00 |
|
Alex Forencich
|
64c1cb1e39
|
eth: Use signal sync module for internal MAC pause handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 16:27:37 -08:00 |
|
Alex Forencich
|
916355ca8a
|
eth: Add TX/RX polarity control to MAC+PHY+GT wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-24 17:17:23 -08:00 |
|
Alex Forencich
|
7047cb5c4f
|
eth: Tie off transceiver control signals during simulation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-24 16:28:59 -08:00 |
|
Alex Forencich
|
f0ec82a384
|
eth: Add MAC+PHY+GT wrapper for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:22:54 -08:00 |
|
Alex Forencich
|
7613cae4f0
|
eth: Use 2D array for PFC config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:08:43 -08:00 |
|
Alex Forencich
|
7f2ecf9b49
|
eth: Implement RX sequence error reporting in MAC+PHY module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 10:16:32 -08:00 |
|
Alex Forencich
|
422c54229e
|
eth: Split block type checks in MAC+PHY to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 10:02:08 -08:00 |
|
Alex Forencich
|
8f6a99112b
|
eth: Add missing block types to MAC+PHY logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 09:55:28 -08:00 |
|
Alex Forencich
|
6a294cef2c
|
Use string type for string parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-21 19:14:28 -08:00 |
|
Alex Forencich
|
17f3613ca4
|
eth: Clean up function definitions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-20 12:21:33 -08:00 |
|
Alex Forencich
|
94dba88560
|
eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:42 -08:00 |
|
Alex Forencich
|
255b26d2f2
|
eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:22 -08:00 |
|
Alex Forencich
|
baa5f72a6c
|
eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:16:54 -08:00 |
|
Alex Forencich
|
ffaf05f2d1
|
eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:05:59 -08:00 |
|
Alex Forencich
|
fab49d1435
|
eth: Add RGMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:50:42 -08:00 |
|
Alex Forencich
|
c0583aaff5
|
eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:37:12 -08:00 |
|
Alex Forencich
|
1dc5463f00
|
eth: Add GMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:34:49 -08:00 |
|
Alex Forencich
|
175230eeaf
|
eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:46:31 -08:00 |
|
Alex Forencich
|
af912cc849
|
eth: Add MII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:05:41 -08:00 |
|
Alex Forencich
|
5c8037093b
|
eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:06:41 -08:00 |
|
Alex Forencich
|
2abe774f8a
|
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:48:54 -08:00 |
|
Alex Forencich
|
90650aee69
|
eth: Add 10G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:47:54 -08:00 |
|
Alex Forencich
|
04b73e7ddf
|
eth: Add 1G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:12:57 -08:00 |
|
Alex Forencich
|
8f8572bdee
|
eth: Add taxi_axis_if to MAC file list files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 15:54:15 -08:00 |
|
Alex Forencich
|
2616e3f3e3
|
eth: Add 10G Ethernet combined MAC+PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:40:50 -08:00 |
|
Alex Forencich
|
0ddb89b18f
|
eth: Add 10G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:26:03 -08:00 |
|
Alex Forencich
|
fa73f9c1d5
|
eth: Add 1G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:25:48 -08:00 |
|
Alex Forencich
|
8d3d703656
|
eth: Add MAC control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 19:59:11 -08:00 |
|
Alex Forencich
|
96e348ac84
|
eth: Invert TX completion output control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 23:24:28 -08:00 |
|