Set language type to verilog

hate vhdl

.gitea/workflows/publish.yaml

@@ -0,0 +1,37 @@
+name: Publish Package
+on: [push]
+
+jobs:
+  build:
+    name: Build Package
+    runs-on: ubuntu-latest
+
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: "3.x"
+      - run: python3 -m pip install build --user
+      - run: python -m build
+      - uses: actions/upload-artifact@v3
+        with:
+          name: python-package-distributions
+          path: dist/
+
+  deploy:
+    name: Deploy Package
+    needs:
+      - build
+    runs-on: ubuntu-latest
+    
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: "3.x"
+      - run: python3 -m pip install twine --user
+      - uses: actions/download-artifact@v3
+        name: python-package-distributions
+        path: dist/ # Does this even do anything?
+      - run: ls -laR python-package-distributions
+      - run: TWINE_PASSWORD=${{ secrets.PYPI_PAT }} TWINE_USERNAME=bslathi19 python -m twine upload --repository-url ${{ vars.CI_API_URL }} python-package-distributions/*

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.2.1"  # REQUIRED, although can be dynamic
+version = "0.5.2"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:
@@ -122,8 +122,8 @@ classifiers = [
 # https://packaging.python.org/discussions/install-requires-vs-requirements/
 dependencies = [
   "pyyaml",
-  "cocotb",
+  "cocotb>=2",
-  "rtl-manifest"
+  "rtl-manifest>=0.3.1"
 ]
 
 # List additional groups of dependencies here (e.g. development

requirements.txt

@@ -1,4 +1,8 @@
+-i https://git.byronlathi.com/api/v4/projects/95/packages/pypi/simple
 setuptools
 wheel
 build
 twine
+cocotb
+rtl-manifest
+pyyaml

src/fpga_sim/fpga_sim.py

@@ -1,11 +1,11 @@
-from ast import parse
-from email.mime import base
 import os
 import sys
 
 import argparse
 
-from cocotb.runner import get_runner
+import subprocess
+
+from cocotb_tools.runner import get_runner, VerilatorControlFile
 
 from rtl_manifest import rtl_manifest
 
@@ -22,6 +22,7 @@ def fpga_sim_main():
 
     parser.add_argument("yaml")
     parser.add_argument("test_name", nargs="?")
+    parser.add_argument("-j", "--jobs", default=1)
 
     args = parser.parse_args()
 
@@ -78,7 +79,9 @@ def fpga_sim_main():
     sim = os.getenv("SIM", "verilator")
     runner = get_runner(sim)
 
-    os.environ["MAKEFLAGS"] = "-j"
+    jobs = args.jobs
+    print(jobs)
+    os.environ["MAKEFLAGS"] = f"-j{jobs}"
 
     tests_to_run = []
 
@@ -92,18 +95,38 @@ def fpga_sim_main():
     # Turn this into a multiprocessing pool
     for test in tests_to_run:
 
-        sources = rtl_manifest.read_sources(f"{test['base_path']}/{test['sources']}")
+        sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
 
-        runner.build(
+        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv")), sources))
-            verilog_sources=sources,
+        verilator_sources = [VerilatorControlFile(s) for s in list(filter(lambda s: (s.endswith(".vlt")), sources))]
-            hdl_toplevel=test["toplevel"],
+
-            build_dir=f"{test['base_path']}/sim_build",
+        sources = []
-            waves=test["waves"],
+        sources.extend(verilog_sources)
-            defines=defines
+        sources.extend(verilator_sources)
-        )
+
+        build_args = ["--timing"]
+
+        # By default, verilator only uses vcd instead of fst, but fst is better.
+        if test["waves"]:
+            build_args.append("--trace-fst")
+
+        try:
+            runner.build(
+                sources=sources,
+                includes=incdirs,
+                hdl_toplevel=test["toplevel"],
+                build_dir=f"{test['base_path']}/sim_build",
+                waves=test["waves"],
+                defines=defines,
+                build_args=build_args
+            )
+        except subprocess.CalledProcessError:
+            print("Failed to compile")
+            return
 
         result_xml = f"../sim_build/{test['name']}_results.xml".replace(" ", "_")
 
         sys.path.append(test["base_path"])
 
-        runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
+        runner.test(hdl_toplevel_lang="verilog", hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
+