For some reason the old one did not want to open in the new version.
Even though the version of the IP is the same, something about it being
made with the old Efinity version made it mad.
I just deleted it and made it again with the same settings and now it
lets me open and configure it.
The pipelining allows the cpu to run at a faster clock speed but results
in latency. At the current 2 MHz, there is 1 cycle of latency which is
negligible because the 6502 cannot do sequential data memory accesses.
In the future, there will have to be some sort of status flag or
interrupt showing that the divider is ready.
Adds a 16x16 divider to go with the multiplier.
The divider is a single stage with no pipelining, which works at the
slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5.
This is acceptable for now but means that the cpu can't be run at 14,
which is the maximum frequency.
This will have to be changed, some things like the VGA connector will
not work because they will interfere with the cpu adapter.
It may be worth thinking about making these smaller and not including
the ethernet for example, since that will not come for a while.
The only things we really need to start are the SD card and serial port.
Don't have the FPGA on the shield, just have it be a board that plugs
into the FPGA.
Don't mind the component and footprint choices yet, I still need to
figure out exactly which parts to use.
Split the project into two parts, the adapter will connect the cpu
directly to the FPGA, and the shield will house all of the peripherals.
I will get the adapter first so that I can get things like sdram
working first, and then make the shield with things like SD card, USB,
maybe even ethernet and VGA. Basically anthing since it's connected to
an FPGA.
I think that previously, I had not actually commited any of this to git.
This adds all of the new effinix stuff that I had been working on for
months.
The gist of all of this is that the intel fpga is expensive and does not
exist, whereas the effinix ones are not as expensive and more existant.
This redoes the project to use the dev board, as well as a custom board
that I may or may not make.
Now that the ROM is just a bootloader and the kernel is stored on the SD
card, we do not need to be constantly changing the ROM.
Disabling the memory editor dramatically reduces compilation time which
will be useful when implementing FPGA features in the future.
The but count should be set to 7 when entering RXDATA. previously it was
not reset or left at 0, which caused the first byte to only have the lsb
set and all other bits to be read incorrectly.
