Alex Forencich
|
5a8ac23922
|
io: Add LED shift register driver module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 15:44:57 -08:00 |
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Alex Forencich
|
916355ca8a
|
eth: Add TX/RX polarity control to MAC+PHY+GT wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-24 17:17:23 -08:00 |
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Alex Forencich
|
7047cb5c4f
|
eth: Tie off transceiver control signals during simulation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-24 16:28:59 -08:00 |
|
Alex Forencich
|
f0ec82a384
|
eth: Add MAC+PHY+GT wrapper for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:22:54 -08:00 |
|
Alex Forencich
|
7613cae4f0
|
eth: Use 2D array for PFC config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:08:43 -08:00 |
|
Alex Forencich
|
7f2ecf9b49
|
eth: Implement RX sequence error reporting in MAC+PHY module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 10:16:32 -08:00 |
|
Alex Forencich
|
422c54229e
|
eth: Split block type checks in MAC+PHY to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 10:02:08 -08:00 |
|
Alex Forencich
|
8f6a99112b
|
eth: Add missing block types to MAC+PHY logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 09:55:28 -08:00 |
|
Alex Forencich
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6a294cef2c
|
Use string type for string parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-21 19:14:28 -08:00 |
|
Alex Forencich
|
6154506c0a
|
axis: Use reset synchronizer module in AXI stream async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-20 12:44:23 -08:00 |
|
Alex Forencich
|
17f3613ca4
|
eth: Clean up function definitions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-20 12:21:33 -08:00 |
|
Alex Forencich
|
94dba88560
|
eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:42 -08:00 |
|
Alex Forencich
|
255b26d2f2
|
eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:22 -08:00 |
|
Alex Forencich
|
baa5f72a6c
|
eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:16:54 -08:00 |
|
Alex Forencich
|
ffaf05f2d1
|
eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:05:59 -08:00 |
|
Alex Forencich
|
fab49d1435
|
eth: Add RGMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:50:42 -08:00 |
|
Alex Forencich
|
c0583aaff5
|
eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:37:12 -08:00 |
|
Alex Forencich
|
1dc5463f00
|
eth: Add GMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:34:49 -08:00 |
|
Alex Forencich
|
175230eeaf
|
eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:46:31 -08:00 |
|
Alex Forencich
|
af912cc849
|
eth: Add MII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:05:41 -08:00 |
|
Alex Forencich
|
da7fe065cc
|
io: Rework generic ODDR implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 19:27:56 -08:00 |
|
Alex Forencich
|
5c8037093b
|
eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:06:41 -08:00 |
|
Alex Forencich
|
e3d8ad8d36
|
io: Add source-synchronous IO modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 15:44:34 -08:00 |
|
Alex Forencich
|
e18a2b3457
|
io: Add generic IDDR and ODDR modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 15:41:56 -08:00 |
|
Alex Forencich
|
fc1e0efad7
|
ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:07:46 -08:00 |
|
Alex Forencich
|
ad0d44616b
|
ptp: Add PTP TD leaf clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 20:18:17 -08:00 |
|
Alex Forencich
|
68c547b219
|
ptp: Minor cleanup in PTP CDC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 20:17:21 -08:00 |
|
Alex Forencich
|
2eaa2f64a2
|
ptp: Add PTP TD PHC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:50:16 -08:00 |
|
Alex Forencich
|
38a150b87a
|
ptp: Add PTP period output module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:06:46 -08:00 |
|
Alex Forencich
|
2abe774f8a
|
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:48:54 -08:00 |
|
Alex Forencich
|
90650aee69
|
eth: Add 10G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:47:54 -08:00 |
|
Alex Forencich
|
d76e810033
|
axis: Fix parameter sizing in AXI stream FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:46:56 -08:00 |
|
Alex Forencich
|
f356fad6fe
|
ptp: Add PTP clock CDC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 12:49:42 -08:00 |
|
Alex Forencich
|
17b4c37a1e
|
ptp: Add PTP clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 10:52:27 -08:00 |
|
Alex Forencich
|
04b73e7ddf
|
eth: Add 1G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:12:57 -08:00 |
|
Alex Forencich
|
8f8572bdee
|
eth: Add taxi_axis_if to MAC file list files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 15:54:15 -08:00 |
|
Alex Forencich
|
2616e3f3e3
|
eth: Add 10G Ethernet combined MAC+PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:40:50 -08:00 |
|
Alex Forencich
|
0ddb89b18f
|
eth: Add 10G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:26:03 -08:00 |
|
Alex Forencich
|
fa73f9c1d5
|
eth: Add 1G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:25:48 -08:00 |
|
Alex Forencich
|
8d3d703656
|
eth: Add MAC control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 19:59:11 -08:00 |
|
Alex Forencich
|
96e348ac84
|
eth: Invert TX completion output control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 23:24:28 -08:00 |
|
Alex Forencich
|
72dabc5a9a
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:23 -08:00 |
|
Alex Forencich
|
2af4e7af3e
|
eth: Add AXI stream 64-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:15 -08:00 |
|
Alex Forencich
|
a375eb342d
|
eth: Add AXI stream 32-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:06 -08:00 |
|
Alex Forencich
|
c914adf9f1
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:02:48 -08:00 |
|
Alex Forencich
|
e3f047d735
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:27:27 -08:00 |
|
Alex Forencich
|
f0f2a25943
|
eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:54 -08:00 |
|
Alex Forencich
|
8046a46680
|
eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:06 -08:00 |
|
Alex Forencich
|
3f501aaac9
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:12:58 -08:00 |
|
Alex Forencich
|
d52aa2f97e
|
axis: Add AXI stream combination async FIFO/adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-06 00:52:04 -08:00 |
|