Alex Forencich
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879b65cc70
|
eth: Normalize CRC register naming in 10G RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 15:54:49 -07:00 |
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Alex Forencich
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d0d6747f88
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eth: Merge lane swapping logic into BASE-R encode logic in 64-bit BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 11:47:21 -07:00 |
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Alex Forencich
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0e2acbf482
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eth: Fix 2D array declarations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 11:02:30 -07:00 |
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Alex Forencich
|
04df834708
|
eth: Optimize frame length enforcement logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-03 15:49:51 -07:00 |
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Alex Forencich
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8257fdf09e
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eth: Remove unused encodings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-03 13:47:52 -07:00 |
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Alex Forencich
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f4e36bd081
|
eth: Optimize padding logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 23:08:11 -07:00 |
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Alex Forencich
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7e629d934f
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Fix TX enable in AXI stream BASE-R TX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 20:44:43 -07:00 |
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Alex Forencich
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159c9d6241
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eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-10-02 16:11:07 -07:00 |
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Alex Forencich
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76d4465081
|
eth: Convert UltraScale wrapper to use unpacked arrays for channels
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-02 16:10:37 -07:00 |
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Alex Forencich
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38ae0c1587
|
eth: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 15:18:23 -07:00 |
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Alex Forencich
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6a5faf9ebf
|
Cast to int instead of using .integer
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 11:25:34 -07:00 |
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Alex Forencich
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40908b1b92
|
Testbench cleanup for cocotb 2.0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 10:59:38 -07:00 |
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Alex Forencich
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553dea534e
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eth/example/HTG_ZRF8: Add example design for HTG-ZRF8-EM and HTG-ZRF8-R2
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-06 07:03:35 -07:00 |
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Alex Forencich
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0d7e0cf590
|
eth/example/ZCU111: Clean up RFDC clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-05 07:30:30 -07:00 |
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Alex Forencich
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6c9026bccf
|
eth/example/HTG9200: Fix refclock frequency in testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-05 07:15:26 -07:00 |
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Alex Forencich
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07ae2ba989
|
eth: Add RFDC to ZCU111 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-24 11:26:14 -07:00 |
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Alex Forencich
|
4c43b68f94
|
eth: Add 6QSFP FMC support to HTG9200 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 16:24:39 -07:00 |
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Alex Forencich
|
cf0ec74849
|
eth: HTG9200 example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-20 06:37:14 -07:00 |
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Alex Forencich
|
d4089096ae
|
example: Add example design for HTG-9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-02 21:19:58 -07:00 |
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Alex Forencich
|
2065151c01
|
eth: Update 10G-only example designs to use 32-bit MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 23:19:30 -07:00 |
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Alex Forencich
|
7031a3f0b1
|
eth: Add 32-bit mode tests for UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 22:19:55 -07:00 |
|
Alex Forencich
|
5b0cae2aac
|
eth: Add 32-bit support to combined MAC+PCS module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:37:34 -07:00 |
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Alex Forencich
|
7b1ae24d95
|
eth: Report framing and bad block errors in 32-bit BASE-R RX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 21:34:42 -07:00 |
|
Alex Forencich
|
fd521a1511
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:50 -07:00 |
|
Alex Forencich
|
295dc2dd23
|
eth: Add 32-bit AXI stream BASE-R RX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:15:09 -07:00 |
|
Alex Forencich
|
ebb8bf0bd4
|
eth: Add 32-bit AXI stream BASE-R TX module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 20:14:30 -07:00 |
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Alex Forencich
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6f5adb1b41
|
eth: Reset pack_seq even if the header is not marked as valid
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 16:32:48 -07:00 |
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Alex Forencich
|
e8cea4c860
|
eth: Use for loop to reduce duplication
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-17 11:50:29 -07:00 |
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Alex Forencich
|
facdc5fe68
|
eth: Remove extraneous constants
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-16 16:01:12 -07:00 |
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Alex Forencich
|
17e48c5f51
|
eth: Support 32-bit mode in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:16:58 -07:00 |
|
Alex Forencich
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6407b4c7f0
|
eth: Support 32-bit sync gearbox in 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:11:26 -07:00 |
|
Alex Forencich
|
ab09ceb891
|
eth: Support 32 bit mode in BASE-R PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 13:00:14 -07:00 |
|
Alex Forencich
|
e6b5cd6ecd
|
eth: Support 32 bit mode in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:56:03 -07:00 |
|
Alex Forencich
|
70c0e3d52a
|
eth: Fix RX BER monitor when gearbox is enabled
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 12:54:01 -07:00 |
|
Alex Forencich
|
2e1619a045
|
eth: Connect and tie off txsequence
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-15 01:20:23 -07:00 |
|
Alex Forencich
|
cc8ec558bf
|
eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-14 22:54:09 -07:00 |
|
Alex Forencich
|
e993a6cfbf
|
eth: Cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 19:38:06 -07:00 |
|
Alex Forencich
|
65eef8b5e8
|
eth: Parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 19:28:21 -07:00 |
|
Alex Forencich
|
eae4d67367
|
eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 17:57:57 -07:00 |
|
Alex Forencich
|
f9041cd9d2
|
eth: Fix multidriven net
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:51:07 -07:00 |
|
Alex Forencich
|
280e5129b8
|
example: Build all MAC variants for ZCU106
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:48:22 -07:00 |
|
Alex Forencich
|
3349561810
|
eth: Remove extraneous defaults
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:45:00 -07:00 |
|
Alex Forencich
|
741615f203
|
eth: Fix parameter name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:40:32 -07:00 |
|
Alex Forencich
|
e846e7f0cd
|
eth: Add gearbox support to 64-bit 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:39:55 -07:00 |
|
Alex Forencich
|
28195390a2
|
eth: Add GBX_CNT to taxi_xgmii_baser_enc_64 testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:35:04 -07:00 |
|
Alex Forencich
|
d4acf48e0a
|
eth: Fix gearbox interface in 10G PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 16:34:44 -07:00 |
|
Alex Forencich
|
0fd4000f69
|
eth: Support both split and combined MAC/PCS in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 14:31:14 -07:00 |
|
Alex Forencich
|
886aa65522
|
eth: Add testbench for taxi_eth_mac_25g_us module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 10:34:43 -07:00 |
|
Alex Forencich
|
98d06954cc
|
eth: Avoid hardcoding clock period
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-13 10:28:53 -07:00 |
|
Alex Forencich
|
4e66dd0f98
|
eth: Rename gearbox start signals to sync
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-06-12 15:45:07 -07:00 |
|