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79ce91669b
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Add IRQ test
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2026-04-30 22:59:21 -07:00 |
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d519943385
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Add RTI
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2026-04-30 22:24:31 -07:00 |
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d1165bc9c9
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Add jsr and rts
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2026-04-30 21:27:59 -07:00 |
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2338d4c720
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Add some more tests
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2026-04-28 22:17:42 -07:00 |
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2a9af9e9dc
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Add indirect indexed
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2026-04-27 23:00:44 -07:00 |
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dfe27d4ec7
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Add indexed indirect
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2026-04-27 21:59:30 -07:00 |
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b31d7490b2
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Add indirect jump
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2026-04-26 22:13:42 -07:00 |
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dc339cb725
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Add absolute indexed indirect
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2026-04-26 21:57:08 -07:00 |
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7164a8172f
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Add test for abs,y
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2026-04-26 21:08:21 -07:00 |
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cb6cac1245
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add absolute,x
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2026-04-26 21:03:53 -07:00 |
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747438a9b6
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Add absolute addressing
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2026-04-26 20:34:11 -07:00 |
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019b84f41d
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Get reset sequence to work
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2026-04-26 19:28:39 -07:00 |
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9476c6a0dd
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Add 32 bit BRK
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2026-04-26 08:53:59 -07:00 |
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06f933fa56
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Factor out verilog-6502 submodule
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2026-04-18 18:55:05 -07:00 |
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db61ca2d74
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Create project
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2026-04-18 18:50:18 -07:00 |
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